公开(公告)号：US6036350A

公开(公告)日：2000-03-14

申请号：US859013

申请日：1997-05-20

Applicant: Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

Inventor： Larry Mennemeier ,  Alexander Peleg ,  Carole Dulong ,  Millind Mittal ,  Benny Eitan ,  Eiichi Kowashi

IPC: G06F7/544 ,  G06F7/00 ,  G06F7/02 ,  G06F7/50

CPC classification number: G06F7/544 ,  G06F2207/3828 ,  G06F2207/5442

Abstract: A technique for sorting packed signed numbers of two operands into maxima and minima operands and solving absolute differences for each pair of corresponding values of maxima and minima. After packing two source operands with a plurality of data elements containing signed values, a greater-than comparison operation is performed on each pair of corresponding numbers in the two operands to determine which is greater. An exclusive-OR mask is generated for use in swapping those values which need to be rearranged so that all maxima are in one operand and all minima are in another operand. Once the sorting of maxima and minima is complete, a packed subtraction operation is then performed by subtracting the minima from corresponding maxima to obtain absolute differences.

Abstract translation: 一种用于将两个操作数的有符号数目的最大值和最小值操作数进行排序并解决每一对最大值和最小值对应值的绝对差异的技术。 在包含具有包含有符号值的多个数据元素的两个源操作数之后，对两个操作数中的每对相应数字执行大于比较的操作，以确定哪个更大。 生成异或掩码以用于交换需要重新排列的那些值，使得所有最大值都在一个操作数中，并且所有最小值都在另一个操作数中。 一旦最大值和最小值的分类完成，则通过从相应的最大值中减去最小值来进行压缩减法运算，以获得绝对差。

公开(公告)号：US5857096A

公开(公告)日：1999-01-05

申请号：US575686

申请日：1995-12-19

Applicant: David Bistry ,  Larry Mennemeier ,  Alexander D. Peleg ,  Carole Dulong ,  Eiichi Kowashi ,  Millind Mittal ,  Benny Eitan

Inventor： David Bistry ,  Larry Mennemeier ,  Alexander D. Peleg ,  Carole Dulong ,  Eiichi Kowashi ,  Millind Mittal ,  Benny Eitan

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/00

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/30112

Abstract: An apparatus (e.g. a microarchitecture of a microprocessor) comprising a plurality of tags associated with a first storage area indicating that locations in the first storage area are either empty or non-empty responsive to execution of floating point instructions which modify data contained in the first storage area. A first circuit is coupled to the plurality of tags which sets only the plurality of tags to an empty state responsive to receipt of a first instruction. The first instruction indicates termination of execution of instructions which operate upon the packed data stored in the first storage area. The apparatus further comprises a second circuit coupled to the plurality of tags for setting the plurality of tags to a non-empty state responsive to receipt of a second instruction (or instructions). The second instruction specifies an operation upon packed data stored in the first storage area. The second circuit further sets the plurality of tags to indicate execution of instructions which operate upon the packed data. This apparatus advantageously provides a architecture (e.g. a microarchitecture for a microprocessor) for clearing the packed data state at the end of executed blocks of packed data instructions to leave the floating point state in a clear condition for subsequent operations (e.g. blocks of executed floating point instructions).

Abstract translation: 包括与第一存储区域相关联的多个标签的装置（例如微处理器的微架构），其指示第一存储区域中的位置是响应于执行浮点指令而为空或非空的，所述浮点指令修改包含在第一存储区域中的数据 储藏区域。 第一电路耦合到响应于接收到第一指令而仅将多个标签设置为空状态的多个标签。 第一指令指示终止对存储在第一存储区域中的打包数据进行操作的指令的执行。 该装置还包括耦合到多个标签的第二电路，用于响应于接收到第二指令（或指令）将多个标签设置为非空状态。 第二指令指定存储在第一存储区域中的压缩数据的操作。 第二电路还设置多个标签以指示对打包数据进行操作的指令的执行。 该装置有利地提供了一种架构（例如，微处理器的微架构），用于在执行的打包数据指令块的结尾处清除打包数据状态，以使浮点状态处于用于后续操作的清晰状态（例如执行浮点的块 说明）。

公开(公告)号：US5852726A

公开(公告)日：1998-12-22

申请号：US574719

申请日：1995-12-19

Applicant: Derrick Lin ,  Romamohan R. Vakkalagadda ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan

Inventor： Derrick Lin ,  Romamohan R. Vakkalagadda ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Millind Mittal ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan

IPC: G06F7/00 ,  G06F9/30 ,  G06F9/305 ,  G06F9/34 ,  G06F9/38 ,  G06F9/455 ,  G06F9/46 ,  G06F9/48 ,  G06F9/00

CPC classification number: G06F9/30123 ,  G06F9/30036 ,  G06F9/30109 ,  G06F9/30134 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

Abstract: A method and apparatus for executing floating point and packed data instructions using a single physical register file that is aliased. According to one aspect of the invention, a processor is provided that includes a decode unit, a mapping unit, and a storage unit. The decode unit is configured to decode instructions and their operands from at least one instruction set including at least a first and second set of instructions. The storage unit includes a physical register file. The mapping unit is configured to map operands used by the first set of instructions to the physical register file in a stack referenced manner. In addition, the mapping unit is configured to map operands used by the second set of instructions to the same physical register file in a non-stack reference manner.

Abstract translation: 一种用于使用别名的单个物理寄存器文件执行浮点和打包数据指令的方法和装置。 根据本发明的一个方面，提供一种包括解码单元，映射单元和存储单元的处理器。 解码单元被配置为从包括至少第一和第二组指令的至少一个指令集解码指令及其操作数。 存储单元包括物理寄存器文件。 映射单元被配置为以堆栈引用的方式将由第一组指令使用的操作数映射到物理寄存器文件。 此外，映射单元被配置为将第二组指令使用的操作数以非堆栈参考方式映射到相同的物理寄存器文件。

公开(公告)号：US5835748A

公开(公告)日：1998-11-10

申请号：US575704

申请日：1995-12-19

Applicant: Doron Orenstein ,  Ofri Wechsler ,  Millind Mittal ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan R. Vakkalagadda

Inventor： Doron Orenstein ,  Ofri Wechsler ,  Millind Mittal ,  Andrew F. Glew ,  Larry M. Mennemeier ,  Alexander D. Peleg ,  David Bistry ,  Carole Dulong ,  Eiichi Kowashi ,  Benny Eitan ,  Derrick Lin ,  Ramamohan R. Vakkalagadda

IPC: G06F9/30 ,  G06F9/302 ,  G06F9/318 ,  G06F9/38 ,  G06F9/00 ,  G06F9/06

CPC classification number: G06F9/30014 ,  G06F9/30036 ,  G06F9/30105 ,  G06F9/30109 ,  G06F9/3012 ,  G06F9/3013 ,  G06F9/30134 ,  G06F9/30192 ,  G06F9/3861

Abstract: A method and apparatus for executing different sets of instructions that cause a processor to perform different data type operations on different physical registers files that logically appear to software as a single aliased register file. According to one aspect of the invention, a processor is provided that includes at least two physical register files--one for executing scalar data type operations and the other for executing packed data type operations. In addition, the processor includes a transition unit that is configured to cause the two physical register files to logically appear to software executing on the processor as a single logical register file.

Abstract translation: 一种用于执行不同指令集的方法和装置，该方法和装置使处理器对不同的物理寄存器文件执行不同的数据类型操作，所述物理寄存器文件作为单个混叠寄存器文件逻辑上显示为软件。 根据本发明的一个方面，提供一种包括至少两个物理寄存器文件的处理器，一个用于执行标量数据类型操作，另一个用于执行打包数据类型操作。 另外，处理器还包括转移单元，其被配置为使两个物理寄存器文件逻辑地出现在处理器上执行的软件作为单个逻辑寄存器文件。

公开(公告)号：US5721892A

公开(公告)日：1998-02-24

申请号：US554625

申请日：1995-11-06

Applicant: Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

Inventor： Alexander Peleg ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan ,  Wolf Witt ,  Carole Dulong ,  Eiichi Kowashi

IPC: G06F7/544 ,  G06F7/38

CPC classification number: G06F9/30036 ,  G06F7/5443 ,  G06F2207/3828

Abstract: A method and apparatus for including in a processor instructions for performing multiply-subtract operations on packed data. In one embodiment, a processor is coupled to a memory. The memory has stored therein a first packed data and a second packed data. The processor performs operations on data elements in said first packed data and said second packed data to generate a third packed data in response to receiving an instruction. At least one of the data elements in this third packed data storing the result of performing a multiply-subtract operation on data elements in the first and second packed data.

Abstract translation: 一种用于在处理器中包括用于对压缩数据进行乘法减法操作的指令的方法和装置。 在一个实施例中，处理器耦合到存储器。 存储器中存储有第一打包数据和第二打包数据。 处理器对所述第一打包数据和所述第二打包数据中的数据元素执行操作，以响应于接收到指令而产生第三打包数据。 该第三打包数据中的至少一个数据元素存储对第一和第二打包数据中的数据元素进行乘法运算的结果。

公开(公告)号：US5719800A

公开(公告)日：1998-02-17

申请号：US497853

申请日：1995-06-30

Applicant: Millind Mittal ,  Robert Valentine

Inventor： Millind Mittal ,  Robert Valentine

IPC: G06F1/32

CPC classification number: G06F9/3842 ,  G06F1/32 ,  G06F9/3001 ,  G06F9/3802 ,  G06F9/3836 ,  G06F9/3857

Abstract: The power consumed within an integrated circuit (IC) is reduced without substantial impact on its performance for typical applications by throttling the performance of particular functional units within the IC. Artificial worst-case power consumption is reduced by throttling down the activity levels of long-duration sequences of high-power operations. The recent utilization levels of particular functional units within an IC are monitored--for example, by computing each functional unit's average duty cycle over its recent operating history. If this activity level is greater than a threshold, then the functional unit is operated in a reduced-power mode. The threshold value is set large enough to allow short bursts of high utilization to occur without impacting performance. The invention allows an integrated circuit to dynamically make the tradeoff between high-speed operation and low-power operation, by throttling back performance of localized functional units when their utilization exceeds a sustainable level. Additionally, this dynamic power/speed tradeoff can be optimized across multiple functional units within an IC or among multiple ICs within a system. Additionally, this dynamic power/speed tradeoff can be altered by providing software control over throttling parameters.

Abstract translation: 集成电路（IC）中消耗的功率通过节流IC内的特定功能单元的性能而降低，对其典型应用的性能没有显着影响。 通过减少大功率操作的长持续时间序列的活动水平来减少人为的最坏情况下的功耗。 例如，通过计算每个功能单元在其最近运行历史上的平均占空比来监视IC内的特定功能单元的最新利用水平。 如果该活动级别大于阈值，则功能单元以降低功率模式运行。 阈值设置得足够大以允许在不影响性能的情况下发生高利用率的短脉冲串。 本发明允许集成电路在其利用率超过可持续水平时通过限制本地化功能单元的性能来动态地在高速操作和低功率操作之间进行权衡。 另外，这种动态功率/速度的折衷可以在IC内或多个系统内的多个功能单元之间进行优化。 另外，通过提供对节流参数的软件控制，可以改变动态功率/速度的权衡。

公开(公告)号：US5675526A

公开(公告)日：1997-10-07

申请号：US756708

申请日：1996-11-26

Applicant: Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

Inventor： Alexander Peleg ,  Yaakov Yaari ,  Millind Mittal ,  Larry M. Mennemeier ,  Benny Eitan

IPC: G06F9/305 ,  G06F5/00 ,  G06F7/52 ,  G06F9/30 ,  G06F9/302 ,  G06F9/38 ,  G06F7/38

CPC classification number: G06F7/53 ,  G06F9/30014 ,  G06F9/30025 ,  G06F9/30036 ,  G06F9/3885 ,  G06F2207/3828 ,  G06F7/49921

Abstract: A processor. The processor includes a decoder being coupled to receive a control signal. The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data multiply operation is to be performed. The processor further includes a circuit being coupled to the decoder. The circuit is for multiplying a first packed data being stored at the first location with a second packed data being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.

Abstract translation: 处理器 处理器包括被耦合以接收控制信号的解码器。 控制信号具有第一源地址，第二源地址，目的地地址和操作字段。 第一个源地址对应于第一个位置。 第二源地址对应于第二位置。 目的地址对应于第三个位置。 操作字段指示要执行一种打包数据乘法运算。 处理器还包括耦合到解码器的电路。 该电路用于将在第一位置处存储的第一打包数据与存储在第二位置处的第二打包数据相乘。 电路还用于将相应的结果打包数据传送到第三位置。

公开(公告)号：US20240232888A1

公开(公告)日：2024-07-11

申请号：US18617142

申请日：2024-03-26

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06Q20/40 ,  G06Q20/32

CPC classification number: G06Q20/4015 ,  G06Q20/325

Abstract: Systems and methods for making payments are described. The method includes transmitting with a first telecommunications device a request for a transaction identification (TID), a payment amount for a financial transaction, and first geographical location data to a payment server. The payment server generating and transmitting the TID to the first telecommunications device. The first telecommunications device communicating the received TID to a second telecommunications device, and the second telecommunications device transmitting the received TID and second geographical location data to the payment server. The payment server comparing the received TID to the generated TID and the first to the second geographical location data, and in response to a match, transmitting back to the second telecommunications device a payment confirmation request. The second telecommunications device transmitting an authorization order to the payment server to release the payment amount to the first telecommunications device.

公开(公告)号：US20200153961A1

公开(公告)日：2020-05-14

申请号：US16740377

申请日：2020-01-10

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: H04M3/493 ,  H04M15/06

Abstract: A computerized method of terminating audio telephone calls that provides the other party with more information as to why the telephone call was terminated. This method, which is particularly useful for computerized smartphones equipped with voice and data channel communications methods, automatically provides the user with a variety of different informative text messages that can be selected by the user and sent to the other party at the time that a voice call is terminated.

公开(公告)号：US20190139035A1

公开(公告)日：2019-05-09

申请号：US16240300

申请日：2019-01-04

Applicant: Millind Mittal

Inventor： Millind Mittal

IPC: G06Q20/38 ,  G06Q20/32

Abstract: Computerized payment method using short, temporary, transaction ID (TID) symbols. Payees (merchants) register their unique ID telecommunications devices (e.g. Smartphone and phone number), and financial institution with a payment server. When a payee initiates a financial transaction by requesting a TID from the server for that amount. The server sends a TID to the payee, which the payee then communicates to the payer (customer). The payer turn relays this TID to the server, which validates the transaction using the payer device. The server then releases funds to the payee. The server can preserve audit records, but security is enhanced because the merchant never directly accesses the customer's financial account. GPS coordinates and/or payer provided Group IDs may also be used to reduce the number of symbols used in the TID. For use case convenience, phone numbers may be used as a type of globally unique Group identification (GroupID).