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    3D Semiconductor Device and Structure
    81.
    发明申请
    3D Semiconductor Device and Structure 审中-公开

    公开(公告)号：US20180269229A1

    公开(公告)日：2018-09-20

    申请号：US15761426

    申请日：2016-09-21

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H01L27/118

    Abstract: A multilevel semiconductor device, the device including: a first level including a first array of first programmable cells and a first control line; a second level including a second array of second programmable cells and a second control line; and a third level including a third array of third programmable cells and a third control line, where the second level overlays the first level, where the third level overlays the second level, where the first programmable cells are self-aligned to the second programmable cells, and where a programmable logic cell includes a plurality of the first programmable cells and a plurality of the second programmable cells.

    3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS
    83.
    发明申请
    3D MEMORY DEVICES AND STRUCTURES WITH MEMORY ARRAYS AND METAL LAYERS 有权

    公开(公告)号：US20250098182A1

    公开(公告)日：2025-03-20

    申请号：US18963630

    申请日：2024-11-28

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H10B80/00 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

    Abstract: A semiconductor device including: a first level including at least four independently controlled first memory arrays, where the first level includes first transistors; a second level disposed on top of the first level, where the second level includes second memory arrays; and a third level disposed on top of the second level, where the third level includes third transistors, at least one metal layer, and third memory arrays; a fourth level disposed on top of the third level, where the fourth level includes fourth transistors, another at least one metal layer, and is bonded to the third level, where the bonded includes metal-to-metal bonding regions, where the first level includes first filled holes, where the second level includes second filled holes; and a via connection through the second level and the third level, and where the fourth level includes at least one SRAM memory array.

    United states 3D memory semiconductor devices and structures with memory cells
    84.
    发明授权
    United states 3D memory semiconductor devices and structures with memory cells 有权

    公开(公告)号：US12225727B2

    公开(公告)日：2025-02-11

    申请号：US18738967

    申请日：2024-06-10

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Eli Lusky

    IPC: H10B43/27 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

    Abstract: A 3D memory device including: a first structure including a plurality of memory cells, where each memory cell of the plurality of memory cells includes at least one memory transistor, where each of the at least one memory transistor includes a source, a drain, and a channel, where the memory cell includes at least one charge trap structure, and where the at least one memory transistor is self-aligned to an overlaying another the at least one memory transistor, both being processed following a same lithography step; and a control level including a memory controller circuit, where the control level includes a plurality of latch sense amplifiers, where the control level is bonded to the first structure, and where the bonded includes hybrid bonding.

    3D semiconductor device and structure with logic and memory
    85.
    发明授权
    3D semiconductor device and structure with logic and memory 有权

    公开(公告)号：US12219769B2

    公开(公告)日：2025-02-04

    申请号：US18738721

    申请日：2024-06-10

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han

    IPC: H10B43/27 ,  H01L23/528 ,  H01L27/02 ,  H01L29/167 ,  H01L29/47 ,  H01L29/78 ,  H01L29/792 ,  H10B41/10 ,  H10B41/20 ,  H10B43/10 ,  H10B43/20 ,  H10B53/20

    Abstract: A 3D semiconductor device including: a first level including a single crystal layer and a memory control circuit including first transistors and at least one cache memory unit; a first metal layer overlaying the single crystal layer; a second metal layer overlaying the first metal layer; a third metal layer overlaying the second metal layer; second transistors disposed atop the third metal layer with at least one including a metal gate; third transistors disposed atop the second transistors; a fourth metal layer atop the third transistors; a memory array including word-lines and at least four memory mini arrays, each including at least four rows by four columns of memory cells, each of the memory cells includes at least one of the second transistors or at least one of the third transistors; a connection path from the fourth metal to the third metal including a via disposed through the memory array.

    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS
    86.
    发明公开
    3D SEMICONDUCTOR DEVICES AND STRUCTURES WITH ELECTRONIC CIRCUIT UNITS 审中-公开

    公开(公告)号：US20240297169A1

    公开(公告)日：2024-09-05

    申请号：US18662468

    申请日：2024-05-13

    Applicant: Monolithic 3D Inc.

    Inventor： Zvi Or-Bach ,  Jin-Woo Han ,  Brian Cronquist

    IPC: H01L27/06

    CPC classification number: H01L27/0688

    Abstract: A 3D device including: a first level including first transistors and a first interconnect; a second level including second transistors and overlaying the first level; at least four electronic circuit units (ECUs); a redundancy circuit, where each of the at least four ECUs includes a first circuit, which includes a portion of the first transistors, where each of the at least four ECUs includes a second circuit, the second circuit including some second transistors, where each of the at least four ECUs includes a vertical connectivity structure which includes pillars, where the pillars provide electrical connections between the first circuit and the second circuit, where each of the at least four ECUs includes at least one memory control circuit and at least one memory array, where the second level is bonded to the first level, and the bonded includes oxide to oxide and metal to metal bonding regions.

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