公开(公告)号：US09639102B2

公开(公告)日：2017-05-02

申请号：US13770982

申请日：2013-02-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H02M3/156 ,  H02M3/157 ,  G05F1/56 ,  G05F1/563 ,  H02M3/158 ,  H02M1/00

CPC classification number: G05F1/563 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for estimating current. A current source is configured to generate a current and a pulsed sense enable signal is generated. An estimate of the current is generated and the estimate of the current is updated based on a first signal that is configured to couple the current source to an electric power supply and a second signal that is configured to couple the current source to aloud. A system includes the current source and a current prediction unit. The current source is configured to generate a current. The current prediction unit is coupled the current source and is configured to generate the estimate of the current and update the estimate of the current based on the first signal and the second signal.

公开(公告)号：US09201434B2

公开(公告)日：2015-12-01

申请号：US13783137

申请日：2013-03-01

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G05F1/00 ,  G05F1/10

CPC classification number: G05F1/10 ,  H02M3/1588 ,  H02M2001/0016 ,  H02M2001/0032 ,  H02M2003/1586 ,  Y02B70/1466 ,  Y02B70/16

Abstract: A system and method are provided for regulating a voltage at a load. A target current is obtained and a number of regulator phases needed to provide the target current to a load is computed based on an efficiency characteristic of the regulator phases. The regulator phases are configured to provide the target current to the load. A multi-phase electric power conversion device comprises at least two regulator phases and a multi-phase control unit. The multi-phase control unit is configured to obtain the target current, compute the number of the regulator phases needed to provide the target current to the load based on the efficiency characteristic of the regulator phases, and configure the regulator phases to provide the target current to the load.

Abstract translation: 提供一种用于调节负载电压的系统和方法。 获得目标电流，并且基于调节器相的效率特性来计算向负载提供目标电流所需的多个调节器相位。 调节器相配置为向负载提供目标电流。 多相电力转换装置包括至少两个调节器相和多相控制单元。 多相控制单元被配置为获得目标电流，基于调节器相的效率特性来计算向负载提供目标电流所需的调节器相位的数量，并且配置调节器相位以提供目标电流 到负载。

公开(公告)号：US20150326255A1

公开(公告)日：2015-11-12

申请号：US14705838

申请日：2015-05-06

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H04B1/04 ,  H04L27/34

CPC classification number: H03F3/2175 ,  H03F1/565 ,  H03F3/193 ,  H03F3/24 ,  H03F3/245 ,  H03F2200/171 ,  H03F2200/387 ,  H03K3/45 ,  H03K2005/00052 ,  H04B1/04 ,  H04B2001/0408 ,  H04L27/3411

Abstract: A system and method are provided for controlling a radio frequency (RF) power amplifier. A magnitude input and a phase input are received for transmission of a RF signal by the RF power amplifier. A digital pulse, having a center position relative to an edge of a reference clock based on the phase input and having a width based on the magnitude input, is generated. The digital pulse is filtered with a resonant matching network to produce the RF signal corresponding to the magnitude input and the phase input.

Abstract translation: 提供了一种用于控制射频（RF）功率放大器的系统和方法。 接收幅度输入和相位输入用于由RF功率放大器传输RF信号。 产生数字脉冲，其基于相位输入具有相对于参考时钟的边缘的中心位置，并且具有基于幅度输入的宽度。 数字脉冲用谐振匹配网络滤波以产生对应于幅度输入和相位输入的RF信号。

公开(公告)号：US09170980B2

公开(公告)日：2015-10-27

申请号：US13973952

申请日：2013-08-22

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Jonah M. Alben ,  John W. Poulton ,  Thomas Hastings Greer, III

IPC: G11C11/40 ,  G06F15/78

CPC classification number: G06F15/7864 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a processor chip, a system functions chip, and an MCM package configured to include the processor chip, the system functions chip, and an interconnect circuit. The processor chip is configured to include a first ground-referenced single-ended signaling interface circuit. A first set of electrical traces manufactured within the MCM package and configured to couple the first single-ended signaling interface circuit to the interconnect circuit. The system functions chip is configured to include a second single-ended signaling interface circuit and a host interface. A second set of electrical traces manufactured within the MCM package and configured to couple the host interface to at least one external pin of the MCM package. In one embodiment, each single-ended signaling interface advantageously implements ground-referenced single-ended signaling.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括处理器芯片，系统功能芯片和被配置为包括处理器芯片，系统功能芯片和互连电路的MCM封装。 处理器芯片被配置为包括第一接地参考的单端信令接口电路。 在MCM封装内制造的第一组电迹线，用于将第一单端信令接口电路耦合到互连电路。 系统功能芯片被配置为包括第二单端信令接口电路和主机接口。 MCM封装中制造的第二组电迹线，用于将主机接口耦合到MCM封装的至少一个外部引脚。 在一个实施例中，每个单端信令接口有利地实现接地参考的单端信令。

公开(公告)号：US09147447B2

公开(公告)日：2015-09-29

申请号：US13844570

申请日：2013-03-15

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Brucek Kurdo Khailany ,  Thomas Hastings Greer, III ,  John W. Poulton

IPC: G11C11/40 ,  G11C7/10

CPC classification number: G11C7/1057 ,  G11C7/1069 ,  H01L2224/0401 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2924/15192 ,  H01L2924/15311

Abstract: A system is provided for transmitting signals. The system comprises a first processing unit, a memory subsystem, and a package. The first processing unit is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. The memory subsystem is configured to include a second GRS interface circuit. The package is configured to include one or more electrical traces that couple the first GRS interface to the second GRS interface, where the first GRS interface circuit and the second GRS interface circuit are each configured to transmit a pulse along one trace of the one or more electrical traces by discharging a capacitor between the one trace and a ground network.

Abstract translation: 提供用于发送信号的系统。 该系统包括第一处理单元，存储器子系统和封装。 第一处理单元被配置为包括第一接地参考单端信令（GRS）接口电路。 存储器子系统被配置为包括第二GRS接口电路。 所述包装被配置为包括将所述第一GRS接口耦合到所述第二GRS接口的一个或多个电迹线，其中所述第一GRS接口电路和所述第二GRS接口电路各自被配置为沿着所述一个或多个 通过在一个迹线和地面网络之间放电电容器的电迹线。

公开(公告)号：US20150102788A1

公开(公告)日：2015-04-16

申请号：US14055819

申请日：2013-10-16

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H02M3/158

CPC classification number: H02M3/158 ,  H02M3/156 ,  H02M2003/1566

Abstract: A system and method are provided for controlling a switching voltage regulator circuit. An energy difference between a stored energy of a switching voltage regulator and a target energy is determined. A control variable of the switching voltage regulator is computed based on the energy difference and the control variable is applied to a current control mechanism of the switching voltage regulator. In one embodiment, the control variable is pulse width of a control signal.

Abstract translation: 提供了用于控制开关电压调节器电路的系统和方法。 确定开关电压调节器的存储能量与目标能量之间的能量差。 基于能量差计算开关电压调节器的控制变量，并且将控制变量应用于开关电压调节器的电流控制机构。 在一个实施例中，控制变量是控制信号的脉冲宽度。

公开(公告)号：US08930862B2

公开(公告)日：2015-01-06

申请号：US13787705

申请日：2013-03-06

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: G06F17/50 ,  H03K19/096

CPC classification number: H03K19/096

Abstract: A system, method, and computer program product for converting a design from edge-triggered docking to two-phase non-overlapping clocking is disclosed. The method includes the steps of replacing an edge-triggered flip-flop circuit that is coupled to a combinational logic circuit with a pair of latches including a first latch circuit and a second latch circuit and determining a midpoint of the combinational logic circuit based on timing information. The second latch circuit is propagated to a midpoint of the combinational logic circuit and two-phase non-overlapping clock signals are provided to the pair of latches.

Abstract translation: 公开了一种用于将设计从边缘触发对接转换为两相非重叠计时的系统，方法和计算机程序产品。 该方法包括以下步骤：将包括第一锁存电路和第二锁存电路的一对锁存器耦合到组合逻辑电路的边沿触发触发器电路替换，并基于定时确定组合逻辑电路的中点 信息。 第二锁存电路被传播到组合逻辑电路的中点，并且两对非重叠时钟信号被提供给该对锁存器。

公开(公告)号：US20140330796A1

公开(公告)日：2014-11-06

申请号：US13887216

申请日：2013-05-03

Applicant: NVIDIA CORPORATION

Inventor： William J. Dally

IPC: G06F17/30

CPC classification number: G06F17/30153

Abstract: A system and method are provided for representing pointers. An encoding type for a pointer structure referenced by a first cell of a data structure is determined. A first field of the pointer structure is encoded to indicate the encoding type. Further, a second field of the pointer structure is encoded according to the encoding type to indicate a location in memory where a cell structure corresponding to a second cell of the data structure is stored.

Abstract translation: 提供了一种用于表示指针的系统和方法。 确定由数据结构的第一单元引用的指针结构的编码类型。 指针结构的第一个字段被编码以指示编码类型。 此外，根据编码类型对指针结构的第二字段进行编码，以指示存储与数据结构的第二单元相对应的单元结构的存储器中的位置。

公开(公告)号：US08866511B2

公开(公告)日：2014-10-21

申请号：US13688175

申请日：2012-11-28

Applicant: NVIDIA Corporation

Inventor： William J. Dally

IPC: H03D13/00 ,  G01R25/00 ,  H03L7/00 ,  H03K5/00

CPC classification number: H03L7/00 ,  G06F1/10 ,  H03K5/00 ,  H03K2005/00104 ,  H03K2005/00241

Abstract: A method and a system are provided for clock phase detection. A first set of delayed versions of a first clock signal is generated and a second set of delayed versions of a second clock signal is generated. The second set of delayed versions of the second clock signal is sampled using the first set of delayed versions of the first clock signal to produce an array of clock samples in a domain corresponding to the first clock signal. At least one edge indication is located within the array of clock samples.

Abstract translation: 提供了一种用于时钟相位检测的方法和系统。 生成第一时钟信号的第一组延迟版本，并且产生第二组第二时钟信号的延迟版本。 使用第一时钟信号的第一组延迟版本对第二时钟信号的第二组延迟版本进行采样，以产生与第一时钟信号对应的域中的时钟采样阵列。 至少一个边缘指示位于时钟采样阵列内。

公开(公告)号：US08854123B1

公开(公告)日：2014-10-07

申请号：US13946980

申请日：2013-07-19

Applicant: NVIDIA Corporation

Inventor： William J. Dally ,  Brucek Kurdo Khailany ,  John W. Poulton ,  Thomas Hastings Greer, III ,  Carl Thomas Gray

IPC: H01L25/00 ,  H05K1/11

CPC classification number: H05K1/11 ,  H04L25/028 ,  H04L25/0292

Abstract: A system of interconnected chips comprising a multi-chip module (MCM) includes a first processor chip, a second processor chip, and an MCM package configured to include the first processor chip, the second processor chip, and an interconnect circuit. The first processor chip is configured to include a first ground-referenced single-ended signaling (GRS) interface circuit. A first set of electrical traces fabricated within the MCM package and configured to couple the first GRS interface circuit to the interconnect circuit. The second processor chip is configured to include a second GRS interface circuit. A second set of electrical traces fabricated within the MCM package and configured to coupled the second GRS interface circuit to the interconnect circuit.

Abstract translation: 包括多芯片模块（MCM）的互连芯片的系统包括第一处理器芯片，第二处理器芯片和被配置为包括第一处理器芯片，第二处理器芯片和互连电路的MCM封装。 第一处理器芯片被配置为包括第一接地参考单端信令（GRS）接口电路。 在MCM封装内制造的第一组电迹线，用于将第一GRS接口电路耦合到互连电路。 第二处理器芯片被配置为包括第二GRS接口电路。 在MCM封装内制造的第二组电迹线，并被配置为将第二GRS接口电路耦合到互连电路。