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公开(公告)号：US20230072674A1
公开(公告)日：2023-03-09
申请号：US17800601
申请日：2021-02-25
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Liji Gopalakrishnan
IPC: G06F3/06
Abstract: Power consumption in a three-dimensional stack of integrated-circuit memory dies is reduced through selective enabling/disabling of physical signaling interfaces in those dies in response to early transmission of chip identifier information relative to command execution.
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公开(公告)号：US11600349B2
公开(公告)日：2023-03-07
申请号：US17226216
申请日：2021-04-09
Applicant: RAMBUS INC.
Inventor： Thomas Vogelsang , William Ng , Frederick A. Ware
Abstract: Embodiments generally relate to integrated circuit devices having through silicon vias (TSVs). In one embodiment, an integrated circuit (IC) device includes a field of TSVs and an address decoder that selectably couples at least one of the TSVs to at least one of a test input and a test evaluation circuit. In another embodiment, a method includes selecting one or more TSVs from a field of TSVs in at least one IC device, and coupling each selected TSV to at least one of a test input and a test evaluation circuit.
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公开(公告)号：US20220357893A1
公开(公告)日：2022-11-10
申请号：US17824665
申请日：2022-05-25
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , Thomas Vogelsang
Abstract: An memory component includes a memory bank and a command interface to receive a read-modify-write command, having an associated read address indicating a location in the memory bank and to either access read data from the location in the memory bank indicated by the read address after an adjustable delay period transpires from a time at which the read-modify-write command was received or to overlap multiple read-modify-write commands. The memory component further includes a data interface to receive write data associated with the read-modify-write command and an error correction circuit to merge the received write data with the read data to form a merged data and write the merged data to the location in the memory bank indicated by the read address.
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公开(公告)号：US20220137843A1
公开(公告)日：2022-05-05
申请号：US17503058
申请日：2021-10-15
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , Steven C. Woo , Michael Raymond Miller
IPC: G06F3/06
Abstract: A memory system includes two or more memory controllers capable of accessing the same dynamic, random-access memory (DRAM), one controller having access to the DRAM or a subset of the DRAM at a time. Different subsets of the DRAM are supported with different refresh-control circuitry, including respective refresh-address counters. Whichever controller has access to a given subset of the DRAM issues refresh requests to the corresponding refresh-address counter. Counters are synchronized before control of a given subset of the DRAM is transferred between controllers to avoid a loss of stored data.
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公开(公告)号：US11284034B2
公开(公告)日：2022-03-22
申请号：US16859243
申请日：2020-04-27
Applicant: Rambus Inc.
Inventor： Jay Endsley , Thomas Vogelsang , Craig M. Smith , Michael Guidash , Alexander C. Schneider
Abstract: Signals representative of total photocharge integrated within respective image-sensor pixels are read out of the pixels after a first exposure interval that constitutes a first fraction of a frame interval. Signals in excess of a threshold level are read out of the pixels after an ensuing second exposure interval that constitutes a second fraction of the frame interval, leaving residual photocharge within the pixels. After a third exposure interval that constitutes a third fraction of the frame interval, signals representative of a combination of at least the residual photocharge and photocharge integrated within the pixels during the third exposure interval are read out of the pixels.
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Patent Agency Ranking
公开(公告)号：US11270741B2
公开(公告)日：2022-03-08
申请号：US17065278
申请日：2020-10-07
Applicant: Rambus Inc.
Inventor： James E. Harris , Thomas Vogelsang , Frederick A. Ware , Ian P. Shaeffer
IPC: G11C7/00 , G11C7/10 , G11C7/08 , G11C5/02 , G11C11/4076 , G11C11/408 , G11C11/4091 , G11C7/06 , G11C7/12 , G11C7/22 , G11C8/08 , G11C8/10
Abstract: Row activation operations within a memory component are carried out with respect to subrows instead of complete storage rows to reduce power consumption. Further, instead of activating subrows in response to row commands, subrow activation operations are deferred until receipt of column commands that specify the column operation to be performed and the subrow to be activated.
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公开(公告)号：US11257539B2
公开(公告)日：2022-02-22
申请号：US16919653
申请日：2020-07-02
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Thomas Vogelsang
IPC: G11C11/00 , G11C11/4093 , G11C11/4094 , G11C11/4076 , G11C11/4097
Abstract: A memory stack comprises at least two memory components. The memory components have a first data link interface and are to transmit signals on a data link coupled to the first data link interface at a first voltage level. A buffer component has a second data link interface coupled to the data link. The buffer component is to receive signals on the second data link interface at the first voltage level. A level shifting latch produces a second voltage level in response to receiving the signals at the second data link interface, where the second voltage level is higher than the first voltage level.
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公开(公告)号：US20220005519A1
公开(公告)日：2022-01-06
申请号：US17376032
申请日：2021-07-14
Applicant: Rambus Inc.
Inventor： Frederick A. Ware , John Eric Linstadt , Brent Steven Haukness , Kenneth L. Wright , Thomas Vogelsang
IPC: G11C11/403 , G11C11/4097 , G11C11/4096 , G11C8/08 , G11C7/10 , G11C7/18 , G11C5/02 , G11C11/408 , G06F12/06 , G11C11/406 , G11C11/409
Abstract: A memory component includes a first memory bank. The first memory bank has a plurality of sub-arrays having sub-rows of memory elements. The memory component includes a write driver, coupled to the first memory bank, to perform a write operation of an entire sub-row of a sub-array. To perform the write operation, the write driver is to load a burst of write data to the memory bank. The memory bank may then activate a plurality of sense amplifiers associated with a plurality of memory elements of the entire sub-row to load the burst of write data to the plurality of sense amplifiers.
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公开(公告)号：US20210335437A1
公开(公告)日：2021-10-28
申请号：US17245491
申请日：2021-04-30
Applicant: Rambus Inc.
Inventor： Ely Tsern , Frederick A. Ware , Suresh Rajan , Thomas Vogelsang
Abstract: A method of operation in an integrated circuit (IC) memory device is disclosed. The method includes refreshing a first group of storage rows in the IC memory device at a first refresh rate. A retention time for each of the rows is tested. The testing for a given row under test includes refreshing at a second refresh rate that is slower than the first refresh rate. The testing is interruptible based on an access request for data stored in the given row under test.
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公开(公告)号：US11114150B2
公开(公告)日：2021-09-07
申请号：US16838646
申请日：2020-04-02
Applicant: Rambus Inc.
Inventor： Thomas Vogelsang , John Eric Linstadt , Liji Gopalakrishnan
IPC: G11C11/408 , G11C11/4094 , G11C11/4091 , G06F13/42
Abstract: A dynamic random access memory (DRAM) component (e.g., module or integrated circuit) can be configured to have multiple rows in the same bank open concurrently. The controller of the component divides the address space of the banks into segments based on row address ranges. These row address ranges do not necessarily correspond to row address ranges of the bank's subarrays (a.k.a. memory array tiles—MATs). When a command is sent to open a row, the controller marks a plurality of the segments as blocked. The controller thereby tracks address ranges in a bank where it will not open a second row unless and until the first row is closed. The memory component may store information about which, and how many, segments should be blocked in response to opening a row. This information may be read by the controller during initialization.
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