公开(公告)号：US09082824B2

公开(公告)日：2015-07-14

申请号：US13907119

申请日：2013-05-31

申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： H01L21/768 ,  H01L23/48 ,  H01L45/00

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76886 ,  H01L21/76895 ,  H01L23/481 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location.

摘要翻译： 制造具有衬底的半导体器件的方法包括在衬底上形成第一互连层，其中第一金属类型的第一金属部分在第一互连层内并且具有第一通孔接口位置。 在第一互连层上形成层间电介质。 层间电介质中的开口形成在第一金属部分的通孔界面位置之上。 在层间电介质上形成第二互连层。 第二金属部分和第一金属类型的通孔在第二互连层内。 通孔形成在开口中以在第一金属部分和第二金属部分之间形成电接触。 通道位于第一个通过接口位置。 第一金属类型的第一植入物与第一通孔接口位置对准。

公开(公告)号：US08972922B2

公开(公告)日：2015-03-03

申请号：US14096051

申请日：2013-12-04

申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： G06F17/50 ,  H01L21/4763 ,  H01L29/40 ,  H01L21/768

CPC分类号： H01L21/76877 ,  G06F17/5077 ,  H01L21/4763 ,  H01L21/76816 ,  H01L23/5226 ,  H01L29/401 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method includes forming a connection between a first metal layer and a second metal layer. The second metal layer is over the first metal layer. A via location for a first via between the first metal layer and the second metal layer is identified. Additional locations for first additional vias are determined. The first additional vias are determined to be necessary for stress migration issues. Additional locations necessary for second additional vias are determined. The second additional vias are determined to be necessary for electromigration issues. The first via and the one of the group consisting of (i) the first additional vias and second additional vias (ii) the first additional vias plus a number of vias sufficient for electromigration issues taking into account that the first additional vias, after taking into account the stress migration issues, still have an effective via number greater than zero.

摘要翻译： 一种方法包括在第一金属层和第二金属层之间形成连接。 第二金属层在第一金属层之上。 识别用于第一金属层和第二金属层之间的第一通孔的通孔位置。 确定第一个额外通孔的附加位置。 第一个额外的通孔被确定为压力迁移问题所必需的。 确定第二个额外通孔所需的附加位置。 第二个额外的通孔被确定为电迁移问题所必需的。 第一个通路和一个组（i）第一个额外的通孔和第二个额外的通孔（ii）第一个额外的通孔加上一些足够电迁移问题的通孔，考虑到第一个额外的通孔， 考虑到压力迁移问题，仍然有效通过数字大于零。

公开(公告)号：US20150040092A1

公开(公告)日：2015-02-05

申请号：US13956044

申请日：2013-07-31

申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： G06F17/50

CPC分类号： G06F17/5072 ,  G06F17/5077 ,  G06F2217/76 ,  H01L23/522 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

摘要： A computer-implemented method of configuring a semiconductor device includes identifying an interconnect having an interconnect path length greater than a stress-induced void formation characteristic length of the semiconductor device, and placing, with a processor, a conductive structure adjacent the interconnect to define a pair of segments of the interconnect. Each segment has a length no greater than the stress-induced void formation characteristic length of the interconnect, and the conductive structure is selected from the group consisting of a decoy via connected to the interconnect, a floating tile disposed along the interconnect, a tab that laterally extends outward from the interconnect, and a jumper from a first metal layer in which the interconnect is disposed to a second metal layer.

摘要翻译： 配置半导体器件的计算机实现的方法包括识别具有大于半导体器件的应力引起的空隙形成特征长度的互连路径长度的互连，以及与处理器相邻配置的导电结构，以定义 互连的一对段。 每个段的长度不大于互连的应力诱导的空隙形成特征长度，并且导电结构选自连接到互连的诱饵通道，沿互连设置的浮动瓦， 横向地从互连件向外延伸，并且从其中布置有互连的第一金属层的跳线到第二金属层。

公开(公告)号：US20150035151A1

公开(公告)日：2015-02-05

申请号：US13956068

申请日：2013-07-31

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  H01L21/768 ,  H01L21/76846 ,  H01L21/76849 ,  H01L23/528 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device includes a substrate, a dielectric layer supported by the substrate, an interconnect adjacent the dielectric layer, the interconnect including a conduction material and a barrier material disposed along sidewalls of the interconnect between the conduction material and the dielectric layer, and a layer disposed over the interconnect to establish an interface between the conduction material, the barrier material, and the layer. A plate is disposed along a section of the interconnect to interrupt the interface.

摘要翻译： 半导体器件包括衬底，由衬底支撑的电介质层，与电介质层相邻的互连，所述互连包括传导材料和沿导电材料和电介质层之间的互连侧壁设置的阻挡材料，以及层 布置在互连上以建立导电材料，阻挡材料和层之间的界面。 沿着互连的一部分布置板以中断接口。

公开(公告)号：US20140353841A1

公开(公告)日：2014-12-04

申请号：US13907119

申请日：2013-05-31

申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

IPC分类号： H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76877 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76886 ,  H01L21/76895 ,  H01L23/481 ,  H01L45/1683 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of making a semiconductor device having a substrate includes forming a first interconnect layer over the substrate, wherein a first metal portion of a first metal type is within the first interconnect layer and has a first via interface location. An interlayer dielectric is formed over the first interconnect layer. An opening in the interlayer dielectric is formed over the via interface location of the first metal portion. A second interconnect layer is formed over the interlayer dielectric. A second metal portion and a via of the first metal type is within the second interconnect layer. The via is formed in the opening to form an electrical contact between the first metal portion and the second metal portion. The via is over the first via interface location. A first implant of the first metal type is aligned to the first via interface location.

摘要翻译： 制造具有衬底的半导体器件的方法包括在衬底上形成第一互连层，其中第一金属类型的第一金属部分在第一互连层内并且具有第一通孔接口位置。 在第一互连层上形成层间电介质。 层间电介质中的开口形成在第一金属部分的通孔界面位置之上。 在层间电介质上形成第二互连层。 第二金属部分和第一金属类型的通孔在第二互连层内。 通孔形成在开口中以在第一金属部分和第二金属部分之间形成电接触。 通道位于第一个通过接口位置。 第一金属类型的第一植入物与第一通孔接口位置对准。

公开(公告)号：US08832624B1

公开(公告)日：2014-09-09

申请号：US13929114

申请日：2013-06-27

申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5077

摘要： A mechanism for determining cumulative process-induced damage due to the antenna effect during formation of an integrated circuit is provided. This cumulative process-induced damage is compared to a cumulative process-induced damage threshold for each layer to determine whether a violation has occurred, or whether cumulative damage below a threshold is such that a more aggressive use of conductive material in a subsequently formed layer can be made. The cumulative damage can also be compared to a cumulative process-induced damage warning threshold at each layer in order to warn a designer that steps should be taken during design/formation of subsequent conductive layers to reduce the cumulative damage. In addition, automated solutions are provided for exceeding either threshold, such as connecting conductive layers at a later stage in processing to avoid charge buildup on the gate dielectric or inclusion of diode devices to leak charge from the interconnect layers.

摘要翻译： 提供了一种用于在集成电路形成期间确定由于天线效应引起的累积过程引起的损坏的机制。 将累积过程诱发的损伤与每个层的累积过程诱发的损伤阈值进行比较，以确定是否发生违规，或者是否低于阈值的累积损伤是否使得随后形成的层中更积极地使用导电材料可以 做成 累积损伤也可以与每层的累积过程引起的损伤警告阈值进行比较，以警告设计者在设计/形成后续导电层期间应采取步骤以减少累积损伤。 此外，提供超过阈值的自动化解决方案，例如在处理中在稍后阶段连接导电层，以避免栅极电介质上的电荷积累或者包含二极管器件从互连层泄漏电荷。

公开(公告)号：US08741719B1

公开(公告)日：2014-06-03

申请号：US13790014

申请日：2013-03-08

申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

IPC分类号： H01L21/8247

CPC分类号： H01L27/11534 ,  H01L27/11524 ,  H01L29/66545

摘要： A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.

摘要翻译： 在NVM区域中形成热生长含氧栅极电介质和选择栅极。 在逻辑区域中形成高k栅极电介质，势垒层和伪栅极。 阻挡层可以包括工作功能设定材料。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介质层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，导致开口。 栅极层形成在NVM区域中的电荷存储层中并且在逻辑区域的开口内，其中开口内的栅极层与势垒层一起在逻辑区域中形成逻辑门，栅极层被图案化 以在NVM区域中形成控制门。

公开(公告)号：US08694926B2

公开(公告)日：2014-04-08

申请号：US13484022

申请日：2012-05-30

申请人： Douglas M Reber ,  Mehul D. Shroff ,  Edward O Travis

发明人： Douglas M Reber ,  Mehul D. Shroff ,  Edward O Travis

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： A technique for computer-aided design layer checking of an integrated circuit design includes generating a representation of a device (e.g., a parameterized cell). Computer-aided design (CAD) layers are sequentially removed from the parameterized cell and a determination is made as to whether expected errors are detected or missed by an associated deck. The associated deck is then modified to detect the expected errors that are missed.

摘要翻译： 用于集成电路设计的计算机辅助设计层检查的技术包括生成设备（例如，参数化单元）的表示。 计算机辅助设计（CAD）层从参数化的单元中顺序地移除，并且确定是否由相关联的卡座检测到或错过预期的错误。 然后修改相关甲板以检测错过的预期错误。

公开(公告)号：US08557650B2

公开(公告)日：2013-10-15

申请号：US12872070

申请日：2010-08-31

申请人： Mehul D. Shroff

发明人： Mehul D. Shroff

IPC分类号： H01L21/8238

CPC分类号： H01L21/28273 ,  H01L21/28123 ,  H01L22/26 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11546

摘要： A dummy gate stack is created in an area different from a region where the non-volatile memory (NVM) array is located. The dummy gate stack is used to simulate an actual NVM gate stack used in the NVM array. During an etch of the NVM gate stack, the dummy gate stack is also etched so that the end of both the stack etches occur at the same time. This allows for improved end point detection of the NVM gate stack etch due to increased endpoint material being exposed at the end of the etch. Also other tiling features may be formed during the etch of the dummy gate stack.

摘要翻译： 在与非易失性存储器（NVM）阵列所在的区域不同的区域中创建虚拟栅极堆叠。 虚拟栅极堆栈用于模拟NVM阵列中使用的实际NVM栅极堆叠。 在NVM栅极堆叠的蚀刻期间，也蚀刻虚拟栅极堆叠，使得两个堆叠蚀刻的结束同时发生。 这允许由于在蚀刻结束时露出的增加的端点材料而改进NVM栅极堆叠蚀刻的终点检测。 在虚拟栅极堆叠的蚀刻期间也可形成其它的平铺特征。

公开(公告)号：US20130267074A1

公开(公告)日：2013-10-10

申请号：US13790004

申请日：2013-03-08

申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, JR.

发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, JR.

IPC分类号： H01L21/82 ,  H01L21/28

CPC分类号： H01L21/82 ,  H01L21/28008 ,  H01L21/28273 ,  H01L21/28282 ,  H01L27/11526 ,  H01L27/11534 ,  H01L27/11536 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/42348 ,  H01L29/51 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

摘要： A thermally-grown oxygen-containing layer is formed over a control gate in an NVM region, and a high-k dielectric layer and barrier layer are formed in a logic region. A polysilicon layer is formed over the oxygen-containing layer and barrier layer and is planarized. A first masking layer is formed over the polysilicon layer and control gate defining a select gate location laterally adjacent the control gate. A second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening at the logic gate location which exposes the barrier layer.

摘要翻译： 在NVM区域的控制栅极上形成热生长含氧层，在逻辑区域形成高k电介质层和阻挡层。 在含氧层和阻挡层上方形成多晶硅层并进行平坦化。 第一掩模层形成在多晶硅层和控制栅极上，该栅极限定了横向邻近控制栅极的选择栅极位置。 形成定义逻辑门位置的第二掩蔽层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以在逻辑门位置处产生暴露阻挡层的开口。