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    Fuse/resistor utilizing interconnect and vias and method of making
    1.
    发明授权
    Fuse/resistor utilizing interconnect and vias and method of making 有权

    公开(公告)号：US09685405B2

    公开(公告)日：2017-06-20

    申请号：US13907497

    申请日：2013-05-31

    申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    IPC分类号： H01L23/525 ,  H01L23/522 ,  H01L49/02

    CPC分类号： H01L23/5256 ,  H01L23/5228 ,  H01L28/20 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor structure comprising a fuse/resistor structure over a functional layer having a substrate. The fuse/resistor structure includes a via, a first interconnect layer, and a second interconnect layer. The via is over the functional layer and has a first end and a second end vertically opposite the first end, wherein the first end is bounded by a first edge and a second edge opposite the first edge and the second end is bounded by a third edge and a fourth edge opposite the third edge. The first interconnect layer includes a first metal layer running horizontally and contacting the first end and completely extending from the first edge to the second edge. The second interconnect layer includes a second metal layer running horizontally and contacting the second end of the via and extending past the third edge but reaching less than half way to the fourth edge.

    METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN
    4.
    发明申请
    METHOD AND SYSTEM FOR DERIVED LAYER CHECKING FOR SEMICONDUCTOR DEVICE DESIGN 有权
    用于半导体器件设计的衍生层检查的方法和系统

    公开(公告)号：US20140040839A1

    公开(公告)日：2014-02-06

    申请号：US13562443

    申请日：2012-07-31

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： G06F17/50

    CPC分类号： G06F17/5081 ,  G03F1/00 ,  G06F19/00 ,  G21K5/00

    摘要： A system and method are provided for enabling a systematic detection of issues arising during the course of mask generation for a semiconductor device. IC mask layer descriptions are analyzed and information is generated that identifies devices formed by active layers in the masks, along with a description of all layers in proximity to the found devices. The IC mask information is compared to a netlist file generated from the initial as-designed schematic. Determinations can then made, for example, as to whether all intended devices are present, any conflicting layers are in proximity to or interacting with the intended devices, and any unintended devices are present in the mask layers. Steps can then be taken to resolve the issues presented by the problematic devices.

    摘要翻译： 提供了一种系统和方法，用于能够系统地检测在半导体器件的掩模生成过程中产生的问题。 分析IC掩模层描述，并生成识别掩模中由有源层形成的设备的信息，以及邻近发现的设备的所有层的描述。 将IC掩模信息与从初始设计原理图生成的网表文件进行比较。 然后可以进行例如关于所有预期设备是否存在的确定，任何冲突的层都与预期设备接近或相互作用，并且任何非预期的设备存在于掩模层中。 然后可以采取步骤来解决有问题的设备提出的问题。

    Via placement and electronic circuit design processing method and electronic circuit design utilizing same
    5.
    发明授权
    Via placement and electronic circuit design processing method and electronic circuit design utilizing same 有权
    通过放置和电子电路设计处理方法及利用电子电路设计

    公开(公告)号：US08595667B1

    公开(公告)日：2013-11-26

    申请号：US13661131

    申请日：2012-10-26

    申请人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    发明人： Mehul D. Shroff ,  Douglas M. Reber ,  Edward O. Travis

    IPC分类号： G06F17/50 ,  G06F9/455

    CPC分类号： G06F17/5072 ,  G06F17/5077

    摘要： A computer-implemented method for processing an electronic circuit design, a method of placing vias within an electronic circuit, and an electronic circuit produced utilizing such method(s) are disclosed. A method embodiment for processing an electronic circuit design comprises accessing, utilizing a computer, data which represents an electronic circuit design, identifying a via metallization feature associated with at least one interconnect metallization feature of the electronic circuit design utilizing data which represents the electronic circuit design. The described method embodiment further comprises evaluating a spacing design rule check on the via metallization feature of the electronic circuit design utilizing an area occupied by the at least one interconnect metallization feature.

    摘要翻译： 公开了一种用于处理电子电路设计的计算机实现的方法，将通孔置于电子电路内的方法以及利用这种方法制造的电子电路。 用于处理电子电路设计的方法实施例包括访问利用计算机的表示电子电路设计的数据，利用代表电子电路设计的数据识别与电子电路设计的至少一个互连金属化特征相关联的通孔金属化特征 。 所描述的方法实施例还包括利用利用至少一个互连金属化特征所占据的面积评估电子电路设计的通孔金属化特征上的间隔设计规则检查。

    SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING
    6.
    发明申请
    SEMICONDUCTOR DEVICE WITH EMBEDDED HEAT SPREADING 有权
    具有嵌入式热传播的半导体器件

    公开(公告)号：US20130264700A1

    公开(公告)日：2013-10-10

    申请号：US13442014

    申请日：2012-04-09

    申请人： EDWARD O. TRAVIS ,  Douglas M. Reber ,  Mehul D. Shroff

    发明人： EDWARD O. TRAVIS ,  Douglas M. Reber ,  Mehul D. Shroff

    IPC分类号： H01L23/34 ,  H01L21/768

    CPC分类号： H01L23/373 ,  H01L21/768 ,  H01L23/3677 ,  H01L23/522 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor device includes a semiconductor substrate and a plurality of clock drivers, wherein the plurality of clock drivers comprises substantially all clock drivers of the semiconductor device, and an interconnect region over the semiconductor substrate, wherein the interconnect region comprises a plurality of heat spreaders, wherein at least 25% of the plurality of clock drivers have a corresponding heat spreader of the plurality of heat spreaders. Each corresponding heat spreader of the plurality of heat spreaders covers at least 50% of a transistor within a corresponding clock driver of the plurality of clock drivers and extends across at least 70% of a perimeter of the transistor within the corresponding clock driver.

    摘要翻译： 半导体器件包括半导体衬底和多个时钟驱动器，其中多个时钟驱动器包括半导体器件的基本上所有的时钟驱动器，以及半导体衬底上的互连区域，其中互连区域包括多个散热器， 其中所述多个时钟驱动器中的至少25％具有所述多个散热器中相应的散热器。 多个散热器的每个相应的散热器覆盖多个时钟驱动器的对应的时钟驱动器内的至少50％的晶体管，并延伸到对应的时钟驱动器内的晶体管的周边的至少70％。

    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit
    8.
    发明授权
    Integrated circuit heater for reducing stress in the integrated circuit material and chip leads of the integrated circuit, and for optimizing performance of devices of the integrated circuit 有权
    集成电路加热器，用于减少集成电路材料中的应力和集成电路的芯片引线，并优化集成电路器件的性能

    公开(公告)号：US09318409B1

    公开(公告)日：2016-04-19

    申请号：US14496870

    申请日：2014-09-25

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L21/66 ,  H01L23/34

    CPC分类号： H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    摘要翻译： 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。

    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT
    9.
    发明申请
    INTEGRATED CIRCUIT HEATER FOR REDUCING STRESS IN THE INTEGRATED CIRCUIT MATERIAL AND CHIP LEADS OF THE INTEGRATED CIRCIT, AND FOR OPTIMIZING PERFORMANCE OF DEVICES OF THE INTEGRATED CIRCUIT 有权
    用于集成电路集成电路材料和芯片引线的集成电路加热器，并优化集成电路器件的性能

    公开(公告)号：US20160093549A1

    公开(公告)日：2016-03-31

    申请号：US14496870

    申请日：2014-09-25

    申请人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Douglas M. Reber ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L23/34

    CPC分类号： H01L25/065 ,  G01K7/00 ,  G01K7/427 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A device comprising a first detector, comprising an output, disposed at a first location of an integrated circuit chip and configured to determine a first temperature information, a chip heater, comprising an input to receive a control signal, disposed at a second location of the integrated circuit and configured to heat an area of the integrated circuit device that includes the first location and the second location, based upon the control signal, and a heater controller comprising a first input coupled to the output of the first detector to receive the first temperature information, and an output coupled to the input of the chip heater, the heater controller configured to generate the control signal based upon the first temperature information.

    摘要翻译： 一种包括第一检测器的装置，包括输出，设置在集成电路芯片的第一位置并且被配置为确定第一温度信息，芯片加热器，包括用于接收控制信号的输入端，所述芯片加热器设置在所述第一温度信息的第二位置处 集成电路并且被配置为基于所述控制信号加热包括所述第一位置和所述第二位置的所述集成电路装置的区域;以及加热器控制器，包括耦合到所述第一检测器的输出的第一输入以接收所述第一温度 信息和耦合到芯片加热器的输入的输出，加热器控制器被配置为基于第一温度信息生成控制信号。