公开(公告)号：US11301405B2

公开(公告)日：2022-04-12

申请号：US16933881

申请日：2020-07-20

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/36 ,  G06F13/362 ,  H01L23/48 ,  H01L23/60 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/50 ,  H01L23/00 ,  G06F13/40 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L27/02

Abstract: This application is directed to a stacked semiconductor device assembly including a plurality of identical stacked integrated circuit (IC) devices. Each IC device further includes a master interface, a channel master circuit, a slave interface, a channel slave circuit, a memory core, and a modal pad configured to receive a selection signal for the IC device to communicate data using one of its channel master circuit or its channel slave circuit. In some implementations, the IC devices include a first IC device and one or more second IC devices. In accordance with the selection signal, the first IC device is configured to communicate read/write data via the channel master circuit of the first IC device, and each of the one or more second IC devices is configured to communicate respective read/write data via the channel slave circuit of the respective second IC device.

公开(公告)号：US11289139B2

公开(公告)日：2022-03-29

申请号：US16793638

申请日：2020-02-18

Applicant: Rambus Inc.

Inventor： Thomas Giovannini ,  Scott C. Best ,  Lei Luo ,  Ian Shaeffer

IPC: G06F12/00 ,  G11C7/22 ,  G11C29/02 ,  G11C29/50 ,  G11C29/56

Abstract: A first timing reference signal and a second timing reference signal are sent to a memory device. The second timing reference signal has approximately a quadrature phase relationship with respect to the first timing reference signal. A plurality of serial data patterns are received from the memory device. The transitions of the first timing reference and the second timing reference determining when transitions occur between the bits of the plurality of data patterns. Timing indicators associated with when received transitions occur between the bits of the plurality of data patterns are received from the memory device. The timing indicators are each measured using a single sampler. Based on the timing indicators, a first duty cycle adjustment for the first timing reference signal, a second duty cycle adjustment for the second timing reference signal, and a quadrature phase adjustment are determined and applied.

公开(公告)号：US11226766B2

公开(公告)日：2022-01-18

申请号：US16947679

申请日：2020-08-12

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

公开(公告)号：US11211114B2

公开(公告)日：2021-12-28

申请号：US16503189

申请日：2019-07-03

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Ely K. Tsern ,  John E. Linstadt ,  Thomas J. Giovannini ,  Scott C. Best ,  Kenneth L. Wright

IPC: G11C5/02 ,  G11C11/4093 ,  G11C5/06 ,  G11C11/4076 ,  G11C11/408 ,  G11C29/00 ,  H01L25/065 ,  H01L25/10 ,  G11C11/4096 ,  H01L25/18 ,  G11C7/10 ,  G11C8/12 ,  H01L23/00

Abstract: A memory system includes dynamic random-access memory (DRAM) components that include interconnected and redundant component data interfaces. The redundant interfaces facilitate memory interconnect topologies that accommodate considerably more DRAM components per memory channel than do traditional memory systems, and thus offer considerably more memory capacity per channel, without concomitant reductions in signaling speeds. Each DRAM component includes multiplexers that allow either of the data interfaces to write data to or read data from a common set of memory banks, and to selectively relay write and read data to and from other components, bypassing the local banks. Delay elements can impose selected read/write delays to align read and write transactions from and to disparate DRAM components.

公开(公告)号：US11024362B2

公开(公告)日：2021-06-01

申请号：US16657658

申请日：2019-10-18

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Suresh Rajan ,  Scott C. Best

IPC: G11C11/4076 ,  G11C11/408 ,  G11C5/04 ,  G11C11/4093 ,  G06F12/06 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22

Abstract: The embodiments described herein describe technologies for using the memory modules in different modes of operation, such as in a standard multi-drop mode or as in a dynamic point-to-point (DPP) mode (also referred to herein as an enhanced mode). The memory modules can also be inserted in the sockets of the memory system in different configurations.

公开(公告)号：US11010098B2

公开(公告)日：2021-05-18

申请号：US16599891

申请日：2019-10-11

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Scott C. Best

IPC: G11C8/00 ,  G06F3/06 ,  G11C5/04 ,  G06F13/16

Abstract: A memory module with multiple memory devices includes a buffer system that manages communication between a memory controller and the memory devices. The memory module additionally includes a command input port to receive command and address signals from a controller and, also in support of capacity extensions, a command relay circuit coupled to the command port to convey the commands and addresses from the memory module to another module or modules. Relaying commands and addresses introduces a delay, and the buffer system that manages communication between the memory controller and the memory devices can be configured to time data communication to account for that delay.

公开(公告)号：US10754799B2

公开(公告)日：2020-08-25

申请号：US16436368

申请日：2019-06-10

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ian Shaeffer

IPC: G06F13/00 ,  G06F13/16 ,  G06F3/06 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/4093

Abstract: A memory system includes a memory controller coupled to multiple memory devices. Each memory device includes an oscillator that generates an internal reference signal that oscillates at a frequency that is a function of physical device structures within the memory device. The frequencies of the internal reference signals are thus device specific. Each memory device develops a shared reference signal from its internal reference signal and communicates the shared reference signal to the common memory controller. The memory controller uses the shared reference signals to recover device-specific frequency information from each memory device, and then communicates with each memory device at a frequency compatible with the corresponding internal reference signal.

公开(公告)号：US10747468B2

公开(公告)日：2020-08-18

申请号：US16543870

申请日：2019-08-19

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F3/06 ,  G11C7/10 ,  G11C5/04

Abstract: A buffer circuit includes a primary interface, a secondary interface, and an encoder/decoder circuit. The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

公开(公告)号：US20200035323A1

公开(公告)日：2020-01-30

申请号：US16537021

申请日：2019-08-09

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  John Eric Linstadt ,  Paul William Roukema

IPC: G11C29/44 ,  G11C29/00 ,  G11C5/04 ,  G11C11/401 ,  G11C29/02 ,  G11C29/52

Abstract: A buffer circuit is disclosed. The buffer circuit includes a command address (C/A) interface to receive an incoming activate (ACT) command and an incoming column address strobe (CAS) command. A first match circuit includes first storage to store failure row address information associated with the memory, and first compare logic. The first compare logic is responsive to the ACT command, to compare incoming row address information to the stored failure row address information. A second match circuit includes second storage to store failure column address information associated with the memory, and second compare logic. The second compare logic is responsive to the CAS command, to compare the incoming column address information to the stored failure column address information. Gating logic maintains a state of a matching row address identified by the first compare logic during the comparison carried out by the second compare logic.

公开(公告)号：US10114775B2

公开(公告)日：2018-10-30

申请号：US15277949

申请日：2016-09-27

Applicant: Rambus Inc.

Inventor： Scott C. Best

IPC: G06F13/362 ,  H01L23/60 ,  H01L25/065 ,  G11C11/408 ,  G11C11/409 ,  H01L23/50 ,  H01L23/00 ,  G06F13/40 ,  G11C11/4096 ,  G11C14/00 ,  G11C16/10 ,  G11C16/26 ,  H01L27/02 ,  H01L23/48

Abstract: This application is directed to a stacked semiconductor device assembly including first and second integrated circuit (IC) devices. Each of the first and second IC devices further includes a master interface, a channel master circuit configured to receive read/write data using the master interface, a slave interface, a channel slave circuit configured to receive read/write data using the slave interface, a memory core coupled to the channel salve circuit, and a modal pad. The first and second IC devices are configured such that in response to at least a modal selection signal received at one of the modal pads of the first and second IC devices, one of the first and second IC devices is configured to receive read/write data using its respective charnel master circuit, and the other of the first and second IC devices is configured to receive read/write data using its respective channel slave circuit.