公开(公告)号：US07451324B2

公开(公告)日：2008-11-11

申请号：US10161500

申请日：2002-05-31

申请人： Rodney W. Schmidt ,  Brian C. Barnes ,  Geoffrey S. Strongin ,  David S. Christie

发明人： Rodney W. Schmidt ,  Brian C. Barnes ,  Geoffrey S. Strongin ,  David S. Christie

IPC分类号： G06F21/22

CPC分类号： G06F21/53 ,  G06F21/71 ,  G06F2221/2153

摘要： A method and system for handling a security exception. The method includes creating a security exception stack frame in secure memory at a base address. The method also includes writing a faulting code sequence address and one or more register values into the security exception stack frame, and executing a plurality of security exception instructions.

摘要翻译： 一种处理安全异常的方法和系统。 该方法包括在基地址的安全存储器中创建安全异常堆栈帧。 该方法还包括将故障代码序列地址和一个或多个寄存器值写入到安全异常堆栈帧中，以及执行多个安全异常指令。

公开(公告)号：US07146477B1

公开(公告)日：2006-12-05

申请号：US10419090

申请日：2003-04-18

申请人： Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Kevin J. McGrath

发明人： Geoffrey S. Strongin ,  David S. Christie ,  William A. Hughes ,  Kevin J. McGrath

IPC分类号： G06F12/00

CPC分类号： G06F12/1475

摘要： A system is configured to selectively block peripheral accesses to system memory. The system includes a secure execution mode (SEM)-capable processor configured to operate in a trusted execution mode. The system also includes a system memory including a plurality of addressable locations. The system further includes a memory controller that may determine a source of an access request to one or more of the plurality of locations of the system memory. The memory controller may further allow the access request to proceed in response to determining that the source of the access request is the SEM-capable processor.

摘要翻译： 系统被配置为选择性地阻止对系统存储器的外围访问。 该系统包括被配置为以可信执行模式操作的安全执行模式（SEM）能力处理器。 该系统还包括包括多个可寻址位置的系统存储器。 系统还包括存储器控制器，其可以确定对系统存储器的多个位置中的一个或多个的访问请求的来源。 响应于确定访问请求的源是具有SEM能力的处理器，存储器控制器还可以允许访问请求继续进行。

公开(公告)号：US06574725B1

公开(公告)日：2003-06-03

申请号：US09431358

申请日：1999-11-01

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G06F940

CPC分类号： G06F9/4843 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3885 ,  G06F15/17381

摘要： A processor architecture containing multiple closely coupled processors in a form of symmetric multiprocessing system is provided. The special coupling mechanism allows it to speculatively execute multiple threads in parallel very efficiently. Generally, the operating system is responsible for scheduling various threads of execution among the available processors in a multiprocessor system. One problem with parallel multithreading is that the overhead involved in scheduling the threads for execution by the operating system is such that shorter segments of code cannot efficiently take advantage of parallel multithreading. Consequently, potential performance gains from parallel multithreading are not attainable. Additional circuitry is included in a form of symmetrical multiprocessing system which enables the scheduling and speculative execution of multiple threads on multiple processors without the involvement and inherent overhead of the operating system. Advantageously, parallel multithreaded execution is more efficient and performance may be improved.

摘要翻译： 提供了一种包含对称多处理系统形式的多个紧密耦合的处理器的处理器架构。 特殊的耦合机制允许它非常有效地推测性地并行地执行多个线程。 通常，操作系统负责在多处理器系统中的可用处理器之间调度各种执行线程。 并行多线程的一个问题是，调度线程以供操作系统执行所涉及的开销使得较短的代码段无法有效地利用并行多线程。 因此，不能实现并行多线程的潜在性能提升。 附加电路包括在对称多处理系统的形式中，其能够在多个处理器上进行多线程的调度和推测执行，而无需操作系统的参与和固有的开销。 有利的是，并行多线程执行更有效率并且可以提高性能。

公开(公告)号：US06456891B1

公开(公告)日：2002-09-24

申请号：US09428614

申请日：1999-10-27

申请人： Uwe Kranich ,  David S. Christie

发明人： Uwe Kranich ,  David S. Christie

IPC分类号： G05B1918

CPC分类号： G06F9/30138 ,  G06F15/7832

摘要： A system and method for transparent handling of extended register states. A set of additional registers, or an extended register file, is added to the base architecture of a microprocessor. The extended register file includes two dedicated registers and a plurality of general-use registers. The extended register file is mapped to a region in main memory. One dedicated register of the extended register file stores the physical base address of the memory region. Another dedicated register of the extended register file is used to store bits to indicate the status of the extended register file. A set of extended instructions is implemented for transferring data to and from the extended register file.

摘要翻译： 一种用于透明处理扩展寄存器状态的系统和方法。 一组附加寄存器或扩展寄存器文件被添加到微处理器的基础架构中。 扩展寄存器文件包括两个专用寄存器和多个通用寄存器。 扩展寄存器文件映射到主存储器中的一个区域。 扩展寄存器文件的一个专用寄存器存储存储器区域的物理基址。 扩展寄存器文件的另一个专用寄存器用于存储位以指示扩展寄存器文件的状态。 实现了一组扩展指令，用于将数据传输到扩展寄存器文件和从扩展寄存器文件传输数据。

公开(公告)号：US06247107B1

公开(公告)日：2001-06-12

申请号：US09055649

申请日：1998-04-06

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/0215 ,  G06F2212/601 ,  G06F2212/6028

摘要： A chipset is configured to communicate between one or more processors and other components of the computer system, including a main memory. The chipset communicates read memory operations initiated by the processors to the main memory, and returns the data provided therefrom to the processors. Additionally, the chipset includes circuitry configured to select a portion of the data and to generate a prefetch address using the data. Accordingly, a pointer included in the data can be used to generate a prefetch address. The prefetching does not rely on observing the data access pattern. Instead, the data being transferred in response to a memory operation is used to generate a prefetch address (i.e. “data-directed prefetching”). In one embodiment, various programmable features are included in the chipset to specify which portion of the data to select, when to perform prefetching, etc. Accordingly, the prefetching mechanism is flexible to adapt to a variety of data structures and patterns of access to those data structures. By implementing the data-directed prefetching algorithm in the chipset, the data can be selected and a prefetch address generated early in the performance of the memory operation. Accordingly, the effective memory latency of the prefetched data may be substantially reduced due to the early initiation of the prefetch operation.

摘要翻译： 芯片组被配置为在计算机系统的一个或多个处理器和其他组件之间进行通信，包括主存储器。 芯片组将由处理器启动的读取存储器操作传送到主存储器，并将从其提供的数据返回到处理器。 另外，芯片组包括被配置为选择数据的一部分并且使用该数据生成预取地址的电路。 因此，可以使用包含在数据中的指针来生成预取地址。 预取不依赖于观察数据访问模式。 相反，使用响应于存储器操作传送的数据来生成预取地址（即“数据定向预取”）。 在一个实施例中，芯片组中包括各种可编程特征，以指定要选择的数据的哪一部分，何时执行预取等。因此，预取机制是灵活的，以适应各种数据结构和对那些 数据结构。 通过在芯片组中实现数据导向预取算法，可以选择数据并在存储器操作性能早期产生预取地址。 因此，由于预取操作的早期启动，预取数据的有效存储器等待时间可能会大大降低。

公开(公告)号：US6157996A

公开(公告)日：2000-12-05

申请号：US969779

申请日：1997-11-13

申请人： David S. Christie ,  Uwe Kranich

发明人： David S. Christie ,  Uwe Kranich

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/32 ,  G06F9/355 ,  G06F9/38

CPC分类号： G06F9/342 ,  G06F9/30072 ,  G06F9/30101 ,  G06F9/30138 ,  G06F9/30185

摘要： A processor for executing computer instructions including, in one embodiment, a machine specific register (MSR) which includes a predicated execution field and an instruction decoder. The decoder is coupled to the MSR and configured to detect predicated execution information contained in the computer instruction and to include conditional execution information in the decoded instruction upon detecting an appropriate setting in the predicated execution field of the MSR. The processor further includes a first execution unit. The first execution unit is configured to detect and evaluate the conditional execution information in the decoded instruction and, if present, to execute the decoded instruction only if a condition represented by the conditional execution information is true. In another embodiment, the processor includes a standard register set and an extended register set, which includes the standard register set. The decoder is configured to search the computer instruction for an extended register indicator upon detecting an appropriate setting in the extended register field of the MSR. The decoder is further configured to fetch, upon detecting the extended register indicator, a value from a selected register within the extended register set. If the decoder detects the absence of extended register indicator, a value is fetched from a selected register where the selected register is within the standard register set. In another embodiment, the MSR includes a three register field and the decoder is configured to interpret the computer instruction as containing first and second source register operands and a destination operand if the instruction contains a three register indicator and the three register field is set appropriately.

摘要翻译： 一种用于执行计算机指令的处理器，在一个实施例中包括机器特定寄存器（MSR），其包括预定执行字段和指令解码器。 解码器耦合到MSR，并被配置为检测计算机指令中包含的预测执行信息，并且在检测到MSR的预测执行字段中的适当设置时，将解码指令中的条件执行信息包括在解码指令中。 处理器还包括第一执行单元。 第一执行单元被配置为仅在由条件执行信息表示的条件为真时才检测和评估解码指令中的条件执行信息，并且如果存在则执行解码指令。 在另一实施例中，处理器包括标准寄存器组和扩展寄存器组，其包括标准寄存器组。 解码器被配置为在MSR的扩展寄存器字段中检测到适当的设置时，在计算机指令中搜索扩展寄存器指示符。 解码器还被配置为在检测到扩展寄存器指示符时，从扩展寄存器组内的选定寄存器获取一个值。 如果解码器检测到没有扩展寄存器指示符，则从选定的寄存器中取出一个值，其中所选寄存器在标准寄存器组内。 在另一个实施例中，MSR包括三个寄存器字段，并且解码器被配置为如果指令包含三个寄存器指示符并且三个寄存器字段被适当地设置，则将该计算机指令解释为包含第一和第二源寄存器操作数以及目标操作数。

公开(公告)号：US6154818A

公开(公告)日：2000-11-28

申请号：US975027

申请日：1997-11-20

申请人： David S. Christie

发明人： David S. Christie

IPC分类号： G06F12/14 ,  G06F13/00

CPC分类号： G06F12/1491

摘要： A system and method for controlling access to privilege partitioned address space for a model specific register file. A superscalar microprocessor includes a plurality of model specific registers (MSRs). MSRs differ between various implementations of a microprocessor architecture. The MSRs are allocated to access regions within a MSR file. Each access region of the MSR file is assigned access attributes. The MSRs are allocated such that the access region and the access attributes of the MSRs are defined by the address of the MSRs. Access to the MSRs is controlled by comparing the address of the MSR to the current privilege level of the microprocessor. In one embodiment, a validity check circuit is used to control access to the MSRs. If an access is attempted to a MSR that cannot be accessed at the current microprocessor privilege level, access to the register is denied and an exception is generated. In one embodiment, an address checker may be used to verify whether a MSR address is within a valid range. The MSR file may be divided into regions, with access granted based on a microprocessor being in a supervisory mode or a user mode.

摘要翻译： 用于控制对特定于模型的寄存器文件的特权分割地址空间的访问的系统和方法。 超标量微处理器包括多个型号特定寄存器（MSR）。 微处理器架构的各种实现之间的MSR不同。 MSR分配给MSR文件中的访问区域。 MSR文件的每个访问区域都被分配访问属性。 分配MSR使得MSR的接入区域和接入属性由MSR的地址定义。 通过将MSR的地址与微处理器的当前特权级别进行比较来控制对MSR的访问。 在一个实施例中，使用有效性检查电路来控制对MSR的访问。 如果尝试对当前微处理器特权级别无法访问的MSR进行访问，则拒绝对寄存器的访问，并生成异常。 在一个实施例中，可以使用地址检查器来验证MSR地址是否在有效范围内。 MSR文件可以被划分为区域，其中基于处于监控模式或用户模式的微处理器被准许访问。

公开(公告)号：US5796974A

公开(公告)日：1998-08-18

申请号：US553204

申请日：1995-11-07

申请人： Michael D. Goddard ,  David S. Christie

发明人： Michael D. Goddard ,  David S. Christie

IPC分类号： G06F9/06 ,  G06F9/22 ,  G06F9/26 ,  G06F9/445 ,  G06F9/30

CPC分类号： G06F9/328 ,  G06F8/66 ,  G06F9/268

摘要： A microcode patching method and apparatus provides for fetching of microcode from an external source which, under appropriate conditions, replaces direct reading of microcode from a microcode ROM. In a decoder having a capability to concurrently dispatch up to four instructions and each dispatch pathway having two alternative decoding pathways including a fastpath pathway and a microcode ROM pathway, a technique and apparatus for patching the microcode ROM is described. This technique and apparatus provides that execution codes from the microcode ROM are selectively replaced, during decoding, by codes taken from an external source, such as from an external memory via a byte queue.

摘要翻译： 微代码修补方法和装置提供从外部源获取微代码，在适当的条件下，代码从微代码ROM直接读取微代码。 在具有同时调度多达四个指令的能力的解码器中，并且每个调度路径具有包括快速路径路径和微码ROM路径的两个备选解码路径，描述了用于修补微代码ROM的技术和装置。 该技术和装置提供了在解码期间通过从外部源（例如从外部存储器经由字节队列）获取的代码来选择性地替换来自微代码ROM的执行代码。

公开(公告)号：US5737629A

公开(公告)日：1998-04-07

申请号：US671439

申请日：1996-06-27

申请人： Gerald D. Zuraski, Jr. ,  Scott A. White ,  Murali S. Chinnakonda ,  David S. Christie

发明人： Gerald D. Zuraski, Jr. ,  Scott A. White ,  Murali S. Chinnakonda ,  David S. Christie

IPC分类号： G06F9/30 ,  G06F9/302 ,  G06F9/312 ,  G06F9/318 ,  G06F9/38

CPC分类号： G06F9/30043 ,  G06F9/30014 ,  G06F9/30036 ,  G06F9/30112 ,  G06F9/30192 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3838 ,  G06F9/384 ,  G06F9/3855 ,  G06F9/3857

摘要： A pipelined or superscalar processor (10) that executes operations utilizing operand data of variable bit widths improves parallel performance by partitioning a fixed bit width operand (200) into several partial operand fields (215, 216 and 217), and checking for data dependencies, tagging and forwarding data in these fields independently of one another. An instruction decoder (18) concurrently dispatches multiple ROPs to various functional units (20, 21, 22 and 80). Conflicts which arise with respect to register resources are resolved through register renaming. However, implementation of register renaming is difficult when register structures are overlapping. The present invention supports independent dependency checking, tagging and forwarding of partial bit fields of a register operand which, in combination, allow renaming of registers. Therefore, the variable width register operand structure greatly assists the processor to resolve data dependencies. Operands are tagged by a reorder buffer (26) and supplied with data when it becomes available without regard for the type of data. This method of dependency resolution supports parallel performance of operations and provides a substantial improvement in overall speed of processing. Thus, the processor promotes parallel processing of operations that act upon overlapping data structures which otherwise resist parallel handling.