利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

317 条记录 (耗时 0.045 秒)

    Rewritable memory device with multi-level, write-once memory cells
    84.
    发明授权
    Rewritable memory device with multi-level, write-once memory cells 有权
    具有多级，一次写入存储单元的可重写存储器件

    公开(公告)号：US08149607B2

    公开(公告)日：2012-04-03

    申请号：US12643561

    申请日：2009-12-21

    申请人： Roy E. Scheuerlein ,  Luca Fasoli

    发明人： Roy E. Scheuerlein ,  Luca Fasoli

    IPC分类号： G11C17/00

    CPC分类号： G11C11/5692 ,  G11C16/349 ,  G11C17/16 ,  G11C2211/5641 ,  G11C2211/5646

    摘要： The embodiments described herein are directed to a memory device with multi-level, write-once memory cells. In one embodiment, a memory device has a memory array comprising a plurality of multi-level write-once memory cells, wherein each memory cell is programmable to one of a plurality of resistivity levels. The memory device also contains circuitry configured to select a group of memory cells from the memory array, and read a set of flag bits associated with the group of memory cells. The set of flag bits indicate a number of times the group of memory cells has been written to. The circuitry is also configured to select a threshold read level appropriate for the number of times the group of memory cells has been written to, and for each memory cell in the group, read the memory cell as an unprogrammed single-bit memory cell or as a programmed single-bit memory cell based on the selected threshold read level.

    摘要翻译： 这里描述的实施例涉及具有多级，一次写入存储器单元的存储器件。 在一个实施例中，存储器装置具有包括多个多级一次写入存储器单元的存储器阵列，其中每个存储器单元可编程为多个电阻率水平中的一个。 存储器件还包含被配置为从存储器阵列中选择一组存储器单元的电路，并且读取与该组存储器单元相关联的一组标志位。 该组标志位指示存储器单元组被写入的次数。 电路还被配置为选择适合于已经写入存储器单元组的次数的阈值读取电平，并且对于组中的每个存储器单元，读取作为未编程的单位存储器单元的存储器单元或者作为 基于所选择的阈值读取电平的编程的单位存储器单元。

    CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY
    85.
    发明申请
    CAPACITIVE DISCHARGE METHOD FOR WRITING TO NON-VOLATILE MEMORY 有权
    用于写入非易失性存储器的电容式放电方法

    公开(公告)号：US20120008373A1

    公开(公告)日：2012-01-12

    申请号：US13237773

    申请日：2011-09-20

    申请人： Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

    发明人： Roy E. Scheuerlein ,  Luca G. Fasoli ,  Tianhong Yan

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

    摘要： A memory system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits for limiting the SET current for the reversible resistance-switching elements. The circuits for limiting the SET current provide a charge on one or more bit lines that is not sufficient to SET the memory cells, and then discharge the bit lines through the memory cells in order to SET the memory cells.

    摘要翻译： 存储器系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储器单元的三维存储器阵列（衬底上方），以及用于限制用于可逆电阻切换的SET电流的电路 元素。 用于限制SET电流的电路在不足以设置存储器单元的一个或多个位线上提供电荷，然后通过存储器单元放电位线以设置存储器单元。

    Semiconductor Memory With Improved Block Switching
    86.
    发明申请
    Semiconductor Memory With Improved Block Switching 有权
    半导体存储器改进块切换

    公开(公告)号：US20120002476A1

    公开(公告)日：2012-01-05

    申请号：US13233602

    申请日：2011-09-15

    申请人： Thomas Yan ,  Luca Fasoli ,  Roy E. Scheuerlein

    发明人： Thomas Yan ,  Luca Fasoli ,  Roy E. Scheuerlein

    IPC分类号： G11C16/26 ,  G11C16/04

    CPC分类号： G11C7/18 ,  G11C13/004 ,  G11C16/24 ,  G11C2029/0411 ,  G11C2213/71 ,  G11C2213/72

    摘要： A non-volatile memory core comprises one or more memory bays. Each memory bay comprises one or more memory blocks that include a grouping of non-volatile storage elements. In one embodiment, memory blocks in a particular memory bay share a group of read/write circuits. During a memory operation, memory blocks are transitioned into active and inactive states. The process of transitioning blocks from an inactive state to an active state includes enabling charge sharing between a memory block entering the active state and another memory block that was previously in the active state. This charge sharing improves performance and/or reduces energy consumption for the memory system.

    摘要翻译： 非易失性存储器核心包括一个或多个存储器空间。 每个存储器托架包括一个或多个存储器块，其包括非易失性存储元件的分组。 在一个实施例中，特定存储器架中的存储器块共享一组读/写电路。 在存储器操作期间，存储器块被转换为活动状态和非活动状态。 将块从非活动状态转换到活动状态的过程包括使得进入活动状态的存储块与先前处于活动状态的另一个存储块之间的电荷共享成为可能。 这种电荷共享提高了存储器系统的性能和/或降低了能量消耗。

    PROGRAMMING NON-VOLATILE STORAGE ELEMENT USING CURRENT FROM OTHER ELEMENT
    87.
    发明申请
    PROGRAMMING NON-VOLATILE STORAGE ELEMENT USING CURRENT FROM OTHER ELEMENT 有权
    使用其他元素的电流编程非易失性存储元件

    公开(公告)号：US20110235405A1

    公开(公告)日：2011-09-29

    申请号：US13154832

    申请日：2011-06-07

    申请人： Roy E. Scheuerlein

    发明人： Roy E. Scheuerlein

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0007 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71 ,  G11C2213/72

    摘要： A non-volatile storage apparatus includes a set of Y lines, a common X line, multiple storage elements each of which is connected to the common X line, and control circuitry in communication with the common X line and the set of Y lines. The multiple data storage elements are capable of being in a first state or a second state. The control circuitry provides control signals to the common X line and the set of Y lines to change a first data storage element of the multiple data storage elements from the first state to the second state by passing a current into the first data storage element from a different Y line through a different storage element. The control circuitry provides control signals to the common X line and the set of Y lines to sequentially change additional data storage elements of the multiple data storage elements from the first state to the second state by passing currents into the additional data storage elements from data storage elements of the multiple data storage elements that were previously changed to the second state and their associated different Y lines.

    摘要翻译： 非易失性存储装置包括一组Y线，公共X线，多个存储元件，每个存储元件连接到公共X线，以及与公共X线和Y线组通信的控制电路。 多个数据存储元件能够处于第一状态或第二状态。 控制电路向公共X线和Y线组提供控制信号，以将多个数据存储元件的第一数据存储元件从第一状态改变到第二状态，通过将电流从第一数据存储元件 不同的Y线通过不同的存储元件。 控制电路向公共X线路和Y线组提供控制信号，以通过将电流从数据存储器传递到附加数据存储元件中来顺序地将多个数据存储元件的附加数据存储元件从第一状态改变到第二状态 先前更改为第二状态的多个数据存储元素的元素及其相关的不同Y行。

    PULSE RESET FOR NON-VOLATILE STORAGE
    88.
    发明申请
    PULSE RESET FOR NON-VOLATILE STORAGE 有权
    非易失性存储器的脉冲复位

    公开(公告)号：US20110235404A1

    公开(公告)日：2011-09-29

    申请号：US13154795

    申请日：2011-06-07

    申请人： Roy E. Scheuerlein

    发明人： Roy E. Scheuerlein

    IPC分类号： G11C11/21

    CPC分类号： G11C13/0007 ,  G11C7/12 ,  G11C7/22 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2013/0092 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/71

    摘要： A non-volatile storage system includes a substrate, control circuitry on the substrate, a three dimensional memory array (above the substrate) that includes a plurality of memory cells with reversible resistance-switching elements, and circuits to SET and RESET the resistance-switching elements. The circuits that RESET the resistance-switching elements provide a pulse to the memory cells that is large enough in magnitude to SET and RESET the memory cells, and long enough to potentially RESET the memory cell but not long enough to SET the memory cells.

    摘要翻译： 非易失性存储系统包括衬底，衬底上的控制电路，包括具有可逆电阻切换元件的多个存储单元的三维存储器阵列（衬底上方），以及用于设置和复位电阻切换 元素。 复位电阻切换元件的电路向存储器单元提供足够大的脉冲以设置和复位存储器单元，并且足够长以潜在地重置存储器单元，但不足以设置存储器单元。