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公开(公告)号：US20160099726A1
公开(公告)日：2016-04-07
申请号：US14866798
申请日：2015-09-25
发明人： Amir Amirkhany
CPC分类号： H04L1/0009 , H04L1/0041 , H04L1/0042 , H04L25/03057 , H04L25/03885
摘要： A method for transmitting an input stream of data across a serial link including a serial channel. The method includes segmenting the stream of data into blocks of bits to form input blocks, and for each input block, calculating a measure of burst error probability, forming an output block and a modification signaling bit from the input block, transmitting the output block, and transmitting the modification signaling bit. The forming of the output block and the modification signaling bit from the input block includes, when the measure of burst error probability exceeds a set threshold: modifying the input block to form the output block, and asserting the modification signaling bit.
摘要翻译： 一种用于在包括串行信道的串行链路上发送输入数据流的方法。 该方法包括将数据流分段成位块以形成输入块，并且对于每个输入块，计算突发错误概率的度量，从输入块形成输出块和修改信令位，发送输出块， 并发送修改信令位。 当突发错误概率的测量值超过设定的阈值时，输出块和修改信令位的形成包括：修改输入块以形成输出块，并且确定修改信令位。
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公开(公告)号：US20150349984A1
公开(公告)日：2015-12-03
申请号：US14697550
申请日：2015-04-27
发明人： Mohammad Hekmat , Amir Amirkhany
IPC分类号： H04L25/03
CPC分类号： H04L25/03057 , H04L2025/03503
摘要： A system for reduced-rate predictive DFE. In one embodiment a plurality of sampler-multiplexer blocks, each including two samplers and a multiplexer-latch, controlled by a multi-phase clock, sample the received analog signal one at a time, and the output of each multiplexer-latch, which may represent the value of the last received bit, is used to control the select input of another multiplexer-latch, so that the other multiplexer-latch selects the appropriate one of two samplers, each applying a different correction to the received analog signal before sampling. Each multiplexer-latch is a clocked element that tracks the data input when the signal at its clock input has a first logic level and retains its output state when its clock input has another (i.e., a second) logic level.
摘要翻译： 一种降低速率预测DFE的系统。 在一个实施例中，多个采样器 - 多路复用器块，每个包括由多相时钟控制的两个采样器和多路复用器锁存器，一次对接收到的模拟信号进行采样，并且每个多路复用器锁存器的输出可以 表示最后接收的位的值，用于控制另一个多路复用器锁存器的选择输入，使得另一个多路复用器锁存器选择两个采样器中适当的一个采样器，每个采样器在采样之前对接收到的模拟信号施加不同的校正。 每个多路复用器锁存器是当其时钟输入处的信号具有第一逻辑电平时跟踪数据输入的时钟元件，并且当其时钟输入具有另一（即第二）逻辑电平时保持其输出状态。
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公开(公告)号：US20150162922A1
公开(公告)日：2015-06-11
申请号：US14550776
申请日：2014-11-21
发明人： Sanquan Song , Amir Amirkhany
CPC分类号： H03L7/0807 , G09G5/008 , H03L7/07 , H03L7/087 , H03L7/0891 , H03L7/091 , H03L7/1072 , H03L7/145 , H04L7/0008 , H04L7/0025 , H04L7/0091 , H04L7/033 , H04L7/0331
摘要： A system for generating a local clock, configurable to utilize a forwarded clock and a data stream, or a data stream only, as frequency and phase references. In one embodiment, the system includes a phase locked loop that may be referenced to a forwarded clock, or to a phase reference formed from received data, utilizing a sampler, a crossing sampler, and a bang-bang phase detector. The system includes a local phase recovery loop which may utilize the bang-bang phase detector as part of a phase detector for controlling a phase interpolator, the output of the phase interpolator serving as the local clock for clocking received data.
摘要翻译： 用于产生本地时钟的系统，可配置为仅将转发的时钟和数据流或数据流用作频率和相位参考。 在一个实施例中，该系统包括可以使用采样器，交叉采样器和爆炸相位检测器参考的转发时钟或由接收数据形成的相位参考的锁相环。 该系统包括局部相位恢复回路，其可以利用爆轰相位检测器作为用于控制相位内插器的相位检测器的一部分，相位内插器的输出用作时钟接收数据的本地时钟。
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公开(公告)号：US08817184B1
公开(公告)日：2014-08-26
申请号：US14180243
申请日：2014-02-13
发明人： Amir Amirkhany , Nasrin Jaffari
CPC分类号： H04L7/0012 , G09G5/008 , G09G2320/0693 , G09G2370/08 , H04L7/0338 , H04L43/087 , H04N5/04
摘要： A system for forwarding a sample rate clock along with data. In one embodiment, a sample rate clock is sent by a transmitter, along with data, to one or more receivers. The receivers sample the received data using the received sampling clock. Delay adjust circuits in the transmitter adjust the delay of each transmitted data stream using delay error sensing and correction implemented in a back channel between the receivers and the transmitter.
摘要翻译： 用于将采样率时钟与数据一起转发的系统。 在一个实施例中，采样率时钟由发射机连同数据发送到一个或多个接收机。 接收机使用接收到的采样时钟对接收到的数据进行采样。 发射机中的延迟调整电路使用在接收机和发射机之间的后向通道中实现的延迟误差感测和校正来调整每个发射数据流的延迟。
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