公开(公告)号：US20090228555A1

公开(公告)日：2009-09-10

申请号：US12044936

申请日：2008-03-08

申请人： Paul A. Joviak ,  Ram Krishnamurthy ,  Julia Pogrebnyak ,  Anuphinh P. Wanderski

发明人： Paul A. Joviak ,  Ram Krishnamurthy ,  Julia Pogrebnyak ,  Anuphinh P. Wanderski

IPC分类号： G06F15/16

CPC分类号： G06Q10/109 ,  G06Q10/107

摘要： A computer-implemented method of automated contact list determination can include detecting a collaborative event in real time and, responsive to detecting the collaborative event, identifying an owner of an electronic message and at least one contact specified by the electronic message, wherein the electronic message is associated with the collaborative event. The contact can be added to a collaborative contact list for the owner. The method can include determining a collaborative ranking for each contact in the collaborative contact list according to a collaborative history between the owner and that contact, selecting a plurality of contacts from the collaborative contact list according to collaborative ranking, and including each of the plurality of contacts within a dynamic address book of the owner.

摘要翻译： 计算机实现的自动联系人列表确定方法可以包括实时地检测协作事件，并且响应于检测协作事件，识别电子消息的所有者和由电子消息指定的至少一个联系人，其中电子消息 与协作事件相关联。 联系人可以添加到所有者的协作联系人列表中。 该方法可以包括根据所有者和该联系人之间的协作历史来确定协作联系人列表中每个联系人的协作排名，根据协作排名从协作联系人列表中选择多个联系人，并且包括多个 所有者的动态地址簿中的联系人。

公开(公告)号：US07161992B2

公开(公告)日：2007-01-09

申请号：US10035574

申请日：2001-10-18

申请人： Mark Anders ,  Ram Krishnamurthy

发明人： Mark Anders ,  Ram Krishnamurthy

IPC分类号： H03K9/00

CPC分类号： H04L25/493 ,  H04L25/0272 ,  H04L25/028 ,  H04L25/0292 ,  H04L25/14

摘要： A transition encoded dynamic bus includes an encoder circuit at the input to the bus and a decoder circuit at the output to the bus. The encoder circuit generates a signal indicative of a transition at the input to the bus rather than the actual value at the input. The decoder circuit decodes the transition encoded information to track the appropriate value to be output from the bus.

摘要翻译： 转换编码的动态总线包括总线输入端的编码器电路和总线输出端的解码器电路。 编码器电路产生指示在总线的输入处的转变而不是输入端的实际值的信号。 解码器电路解码转换编码信息以跟踪从总线输出的适当值。

公开(公告)号：US20060109028A1

公开(公告)日：2006-05-25

申请号：US11314236

申请日：2005-12-22

申请人： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehia Ismail

发明人： Maged Ghoneima ,  Peter Caputa ,  Muhammad Khellah ,  Ram Krishnamurthy ,  James Tschanz ,  Yibin Ye ,  Vivek De ,  Yehia Ismail

IPC分类号： H03K19/173

CPC分类号： G06F13/4072 ,  Y02D10/14 ,  Y02D10/151

摘要： An interconnect architecture is provided to reduce power consumption. A first driver may drive signals on a first interconnect and a second driver may drive signals on a second interconnect. The first driver may be powered by a first voltage and the second driver may be powered by a second voltage different than the first voltage.

公开(公告)号：US20050141599A1

公开(公告)日：2005-06-30

申请号：US10744085

申请日：2003-12-24

申请人： Steven Hsu ,  Ram Krishnamurthy ,  Gian Gerosa

发明人： Steven Hsu ,  Ram Krishnamurthy ,  Gian Gerosa

IPC分类号： H04B3/36

CPC分类号： H04B3/36 ,  H03K3/35625

摘要： A system is provided that includes a clocking circuit to provide two repeater clock signals and a flop repeater circuit to receive the two repeater clock signals and an input data signal. The flop repeater circuit to provide an output data signal based on the two repeater clock signals. The flop repeater circuit including a plurality of transistors and inverters coupled together to function as a flip-flop circuit that passes data without any full transmission gates.

摘要翻译： 提供了一种系统，其包括用于提供两个中继器时钟信号的时钟电路和用于接收两个中继器时钟信号的触发中继器电路和输入数据信号。 触发中继器电路基于两个中继器时钟信号提供输出数据信号。 包括耦合在一起的多个晶体管和反相器的触发中继器电路用作在没有任何全传输门的情况下传递数据的触发器电路。

公开(公告)号：US20050068801A1

公开(公告)日：2005-03-31

申请号：US10676985

申请日：2003-09-30

申请人： Bhaskar Chatterjee ,  Steven Hsu ,  Sriram Vangal ,  Ram Krishnamurthy

发明人： Bhaskar Chatterjee ,  Steven Hsu ,  Sriram Vangal ,  Ram Krishnamurthy

IPC分类号： G11C7/12 ,  G11C8/10 ,  G11C5/06 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C8/10

摘要： A register file contains a local bit trace and a driving signal trace as well as a plurality of data cells coupled to the local bit trace. A device is coupled to the driving signal trace and the local bit trace to intelligently charge and float the local bit trace. The intelligent charging and floating is facilitated by determination of a selection of one of the data cells.

摘要翻译： 寄存器文件包含本地位跟踪和驱动信号跟踪以及耦合到本地位跟踪的多个数据单元。 一个器件耦合到驱动信号跟踪和本地位跟踪，以智能地对本地位跟踪进行充电和浮动。 通过确定数据单元之一的选择来促进智能充电和浮动。

公开(公告)号：US06844750B2

公开(公告)日：2005-01-18

申请号：US10401792

申请日：2003-03-31

申请人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

发明人： Steven K. Hsu ,  Ram Krishnamurthy ,  Chris Hyung-il Kim

IPC分类号： G01R31/30 ,  G11C29/50 ,  G01R31/02

CPC分类号： G11C29/50 ,  G01R31/3012 ,  G11C2029/5004 ,  G11C2029/5006

摘要： A current mirror multi-channel leakage monitor circuit and method measures die leakage and generates digital keeper control bits to control a process compensated dynamic circuit. The leakage monitor enables high resolution on-chip leakage measurements in multiple locations on a die, thereby saving test time and enabling both die to die and within die process compensation.

摘要翻译： 电流镜多通道泄漏监控电路和方法测量管芯泄漏，并产生数字保持器控制位以控制过程补偿动态电路。 泄漏监测器可在芯片上的多个位置进行高分辨率片上泄漏测量，从而节省测试时间，并使裸片和裸片工艺补偿均可实现。

公开(公告)号：US06573756B2

公开(公告)日：2003-06-03

申请号：US09919785

申请日：2001-07-31

申请人： Sanu K. Mathew ,  Mark Anders ,  Ram Krishnamurthy

发明人： Sanu K. Mathew ,  Mark Anders ,  Ram Krishnamurthy

IPC分类号： H03K1716

CPC分类号： H03K19/0963 ,  H03K19/00361

摘要： A noise canceling circuit is provided in a dynamic circuit that includes a high fan-in domino gate. The noise canceling circuit decouples noise from neighboring wires in the dynamic circuit that is injected into a wire that controls the domino gate.

摘要翻译： 在包括高扇形多米诺式门的动态电路中提供噪声消除电路。 噪声消除电路将注入到控制多米诺骨牌的导线的动态电路中的相邻导线的噪声去耦。

公开(公告)号：US06510092B1

公开(公告)日：2003-01-21

申请号：US09943167

申请日：2001-08-30

申请人： Sanu K. Mathew ,  Ram Krishnamurthy

发明人： Sanu K. Mathew ,  Ram Krishnamurthy

IPC分类号： G11C700

CPC分类号： G11C7/12

摘要： A method and apparatus to improve register file performance. In various embodiments, a shadow bitline runs parallel to a local bitline in a register file, and the shadow bitline is coupled to a subset of the data cells to which the local bitline is coupled. In operation, a static keeper holds the local bitline in a condition complementary to the condition of the shadow bitline, when appropriate.

摘要翻译： 一种提高寄存器文件性能的方法和装置。 在各种实施例中，阴影位线平行于寄存器文件中的本地位线运行，并且阴影位线耦合到本地位线耦合到的数据单元的子集。 在操作中，静态保持器在适当时将局部位线保持在与阴影位线的条件互补的条件下。

公开(公告)号：US06441648B1

公开(公告)日：2002-08-27

申请号：US09852442

申请日：2001-05-09

申请人： Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

发明人： Steven K. Hsu ,  Shih-Lien L. Lu ,  Ram Krishnamurthy

IPC分类号： H03K1901

CPC分类号： H03K19/0963

摘要： A double data rate dynamic logic gate in which an evaluation phase is performed for each phase of a clock signal. In one embodiment, an nMOSFET pull-down logic unit is clocked by two nMOSFETs switched in complementary fashion, and dynamic latches provide the output signals. In another embodiment, two nMOSFET pull-down logic units are employed, each clocked by an nMOSFET in complementary fashion, and a static logic unit provides the output signals.

摘要翻译： 一种双数据速率动态逻辑门，其中对时钟信号的每个相位执行评估阶段。 在一个实施例中，nMOSFET下拉逻辑单元由以互补方式切换的两个nMOSFET计时，并且动态锁存器提供输出信号。 在另一个实施例中，采用两个nMOSFET下拉逻辑单元，每个以互补方式由nMOSFET计时，并且静态逻辑单元提供输出信号。

公开(公告)号：US20190056885A1

公开(公告)日：2019-02-21

申请号：US16160482

申请日：2018-10-15

申请人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

发明人： Amrita Mathuriya ,  Sasikanth Manipatruni ,  Victor Lee ,  Huseyin Sumbul ,  Gregory Chen ,  Raghavan Kumar ,  Phil Knag ,  Ram Krishnamurthy ,  IAN YOUNG ,  Abhishek Sharma

IPC分类号： G06F3/06 ,  G06F12/0802 ,  G06F12/1081 ,  G06N3/04

摘要： The present disclosure is directed to systems and methods of implementing a neural network using in-memory, bit-serial, mathematical operations performed by a pipelined SRAM architecture (bit-serial PISA) circuitry disposed in on-chip processor memory circuitry. The on-chip processor memory circuitry may include processor last level cache (LLC) circuitry. The bit-serial PISA circuitry is coupled to PISA memory circuitry via a relatively high-bandwidth connection to beneficially facilitate the storage and retrieval of layer weights by the bit-serial PISA circuitry during execution. Direct memory access (DMA) circuitry transfers the neural network model and input data from system memory to the bit-serial PISA memory and also transfers output data from the PISA memory circuitry to system memory circuitry. Thus, the systems and methods described herein beneficially leverage the on-chip processor memory circuitry to perform a relatively large number of vector/tensor calculations without burdening the processor circuitry.