公开(公告)号：US12099921B2

公开(公告)日：2024-09-24

申请号：US17367633

申请日：2021-07-06

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/065 ,  G06F17/16 ,  G06N3/04

CPC classification number: G06N3/065 ,  G06F17/16 ,  G06N3/04

Abstract: Numerous embodiments of decoders for use with a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The decoders include bit line decoders, word line decoders, control gate decoders, source line decoders, and erase gate decoders. In certain embodiments, a high voltage version and a low voltage version of a decoder is used.

公开(公告)号：US20240112736A1

公开(公告)日：2024-04-04

申请号：US18536186

申请日：2023-12-11

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly ,  Nhan Do ,  Mark Reiten

IPC: G11C16/08 ,  G11C11/54 ,  G11C16/24

CPC classification number: G11C16/08 ,  G11C11/54 ,  G11C16/24 ,  G11C2216/04

Abstract: In one example, a non-volatile memory system, comprises an array of non-volatile memory cells arranged in rows and columns, each non-volatile memory cell comprising a source and a drain; a plurality of bit lines, each of the plurality of bit lines coupled to the drain or each non-volatile memory cell in a column of non-volatile memory cells; a source line coupled to the source of each non-volatile memory cell; and an adaptive bias decoder for providing a voltage to the source line of the array during operation.

公开(公告)号：US11908513B2

公开(公告)日：2024-02-20

申请号：US18103383

申请日：2023-01-30

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari

IPC: G11C11/54 ,  G11C16/04 ,  G06N3/063 ,  G11C16/26 ,  G11C16/28 ,  H03F3/00 ,  H03M1/16 ,  G06N3/065 ,  H03M1/38

CPC classification number: G11C11/54 ,  G06N3/063 ,  G06N3/065 ,  G11C16/0416 ,  G11C16/0425 ,  G11C16/26 ,  G11C16/28 ,  H03F3/005 ,  H03M1/164 ,  H03M1/38

Abstract: Numerous embodiments of analog neural memory arrays are disclosed. In one embodiment, a system comprises a first array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W+ values, and wherein one of the columns in the first array is a dummy column; and a second array of non-volatile memory cells, wherein the cells are arranged in rows and columns and the non-volatile memory cells in one or more of the columns stores W− values, and wherein one of the columns in the second array is a dummy column; wherein pairs of cells from the first array and the second array store a differential weight, W, according to the formula W=(W+)−(W−).

公开(公告)号：US20230229903A1

公开(公告)日：2023-07-20

申请号：US18125703

申请日：2023-03-23

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Stephen Trinh ,  Anh Ly

IPC: G06N3/00 ,  G11C11/54 ,  G11C7/10 ,  G11C8/10 ,  G11C7/12

CPC classification number: G06N3/065 ,  G11C11/54 ,  G11C7/1069 ,  G11C7/1096 ,  G11C8/10 ,  G11C7/12

Abstract: Numerous embodiments are disclosed for splitting a physical array into multiple arrays for separate vector-by-matrix multiplication (VMM) operations. In one example, a system comprises an array of non-volatile memory cells arranged into rows and columns; and a plurality of sets of output lines, where each column contains a set of output lines; wherein each row is coupled to only one output line in the set of output lines for each column.

公开(公告)号：US20220405564A1

公开(公告)日：2022-12-22

申请号：US17893075

申请日：2022-08-22

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. In one example, a method comprises programming a plurality of analog neural non-volatile memory cells in an array of analog neural non-volatile memory cells to store one of N different values, where N is a number of different levels that can be stored in any of the analog neural non-volatile memory cells; measuring a current drawn by the plurality of analog neural non-volatile memory cells; comparing the measured current to a target value; and identifying the plurality of the analog neural non-volatile memory cells as bad if the difference between the measured value and the target value exceeds a threshold.

公开(公告)号：US20220319619A1

公开(公告)日：2022-10-06

申请号：US17839294

申请日：2022-06-13

Applicant: Silicon Storage Technology, Inc,

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/34 ,  G11C16/10 ,  G06N3/063 ,  G06F3/06 ,  G06N3/08 ,  G11C16/26 ,  G11C29/10

Abstract: Circuitry and methods are disclosed for compensating for leakage in analog neural memory in deep learning artificial neural networks. In one example, a method is disclosed of compensating for leakage in an array of analog neural non-volatile memory cells, wherein the array is arranged in rows and columns, wherein each row is coupled to a word line and each column is coupled to a bitline, the method comprising measuring leakage for a column of analog neural non-volatile memory cells coupled to a bitline; storing the measured leakage value; and applying the measured leakage value during a read operation of the column of analog neural non-volatile memory cells to compensate for the leakage.

公开(公告)号：US11449741B2

公开(公告)日：2022-09-20

申请号：US16569647

申请日：2019-09-12

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stephen Trinh ,  Stanley Hong ,  Anh Ly ,  Steven Lemke ,  Nha Nguyen ,  Vipin Tiwari ,  Nhan Do

IPC: G06N3/063 ,  G06N3/04 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34 ,  G11C16/08

Abstract: Testing circuitry and methods are disclosed for use with analog neural memory in deep learning artificial neural networks. The analog neural memory comprises one or more arrays of non-volatile memory cells. The testing circuitry and methods can be utilized during sort tests, qualification tests, and other tests to verify programming operations of one or more cells.

公开(公告)号：US11354562B2

公开(公告)日：2022-06-07

申请号：US15936983

申请日：2018-03-27

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Stanley Hong ,  Anh Ly ,  Thuan Vu ,  Hien Pham ,  Kha Nguyen ,  Han Tran

IPC: G06N3/04 ,  G06F17/16 ,  G06N3/063 ,  G06N3/08 ,  G11C16/04 ,  G11C11/54 ,  H03F3/45

Abstract: Numerous embodiments for processing the current output of a vector-by-matrix multiplication (VMM) array in an artificial neural network are disclosed. The embodiments comprise a summer circuit and an activation function circuit. The summer circuit and/or the activation function circuit comprise circuit elements that can be adjusted in response to the total possible current received from the VMM to optimize power consumption.

公开(公告)号：US20210210144A9

公开(公告)日：2021-07-08

申请号：US16574059

申请日：2019-09-17

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Anh Ly ,  Thuan Vu ,  Hung Quoc Nguyen

IPC: G11C16/12 ,  G11C16/04 ,  G11C16/24

Abstract: An improved method and apparatus for programming advanced nanometer flash memory cells is disclosed. In one embodiment, a programming circuit comprises a switch configured to couple a current source to a capacitor during a first mode and to uncouple the current source from the capacitor during the second mode, wherein during the second mode the capacitor is coupled to the gate of a transistor used to program a memory cell.

公开(公告)号：US10650893B2

公开(公告)日：2020-05-12

申请号：US16550248

申请日：2019-08-25

Applicant: Silicon Storage Technology, Inc.

Inventor： Hieu Van Tran ,  Thuan Vu ,  Stanley Hong ,  Anh Ly ,  Vipin Tiwari ,  Nhan Do

IPC: G11C16/04 ,  H01L27/11521 ,  H01L29/788 ,  G06N3/08

Abstract: Numerous embodiments are disclosed for a high voltage generation algorithm and system for generating high voltages necessary for a particular programming operation in analog neural memory used in a deep learning artificial neural network. Different calibration algorithms and systems are also disclosed. Compensation measures are utilized to compensate for changes in voltage or current as the number of cells being programmed changes.