公开(公告)号：US20080290398A1

公开(公告)日：2008-11-27

申请号：US11904470

申请日：2007-09-26

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28123 ,  H01L21/28167 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/045 ,  H01L29/42324

Abstract: A nonvolatile charge trap memory device and a method to form the same are described. The device includes a channel region having a channel length with crystal plane orientation. The channel region is between a pair of source and drain regions and a gate stack is disposed above the channel region.

Abstract translation: 描述了一种非易失性电荷陷阱存储器件及其形成方法。 该器件包括具有<100>晶面取向的通道长度的沟道区域。 沟道区域位于一对源极区和漏极区之间，栅极堆叠设置在沟道区的上方。

公开(公告)号：US07396773B1

公开(公告)日：2008-07-08

申请号：US10313283

申请日：2002-12-06

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/302

CPC classification number: H01L21/32137 ,  C11D7/261 ,  C11D7/263 ,  C11D7/3218 ,  C11D7/3227 ,  C11D11/0047 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/28247 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/32136

Abstract: A method of making a semiconductor structure, comprises cleaning a gate stack with a cleaning solution. The gate stack comprises a gate layer, a metallic layer on the gate layer, and a etch-stop layer on the metallic layer. The gate layer is on a semiconductor substrate, the cleaning solution is a non-oxidizing cleaning solution, and the metallic layer comprises an easily oxidized metal.

Abstract translation: 一种制造半导体结构的方法，包括用清洁溶液清洗栅极堆叠。 栅极堆叠包括栅极层，栅极层上的金属层和金属层上的蚀刻停止层。 栅极层位于半导体基板上，清洗液为非氧化性清洗液，金属层由容易氧化的金属构成。

公开(公告)号：US07365403B1

公开(公告)日：2008-04-29

申请号：US10074884

申请日：2002-02-13

Applicant: Krishnaswamy Ramkumar

Inventor： Krishnaswamy Ramkumar

IPC: H01L27/108

CPC classification number: H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dielectric thickness of less than approximately 20 angstroms.

Abstract translation: 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可以用于形成包括具有小于约20埃的电等效氧化物栅极介电厚度的氧化物 - 氮化物栅极电介质的半导体器件。

公开(公告)号：US06969689B1

公开(公告)日：2005-11-29

申请号：US10184715

申请日：2002-06-28

Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor ,  Biju Parameshwaran ,  Loren Lancaster

IPC: H01L21/28 ,  H01L21/31 ,  H01L21/314 ,  H01L21/469 ,  H01L21/8246 ,  H01L27/115

CPC classification number: H01L27/11568 ,  H01L21/28282 ,  H01L21/3144 ,  H01L27/115

Abstract: A method of forming oxide-nitride-oxide (ONO) dielectric of a SONOS-type nonvolatile storage device is disclosed. According to a first embodiment, a method may include the steps of forming a tunneling dielectric (step 102), forming a charge storing dielectric (step 104), and forming a top insulating layer (step 106) all in the same wafer processing tool. According to various aspects of the embodiments, all layers of an ONO dielectric of a SONOS-type device may be formed in the same general temperature range. Further, a tunneling dielectric may include a tunnel oxide formed with a long, low pressure oxidation, and a top insulating layer may include silicon dioxide formed with a preheated source gas.

Abstract translation: 公开了一种形成SONOS型非易失性存储装置的氧化物 - 氧化物 - 氧化物（ONO）电介质的方法。 根据第一实施例，一种方法可以包括以下步骤：形成隧道电介质（步骤102），形成电荷存储电介质（步骤104），以及在相同的晶片处理工具中形成顶部绝缘层（步骤106）。 根据实施例的各个方面，SONOS型器件的ONO电介质的所有层可以形成在相同的一般温度范围内。 此外，隧道电介质可以包括形成有长的低压氧化的隧道氧化物，并且顶部绝缘层可以包括用预热的源气体形成的二氧化硅。

公开(公告)号：US06869850B1

公开(公告)日：2005-03-22

申请号：US10326525

申请日：2002-12-20

Applicant: Alain Blosse ,  Krishnaswamy Ramkumar

Inventor： Alain Blosse ,  Krishnaswamy Ramkumar

IPC: H01L21/60 ,  H01L29/417 ,  H01L21/336

CPC classification number: H01L21/76897 ,  H01L29/41775 ,  H01L29/41783

Abstract: In one embodiment, a transistor comprises raised structures over a source region and a drain region. The raised source structures may comprise selectively deposited metal, such as selective tungsten. A self-aligned contact structure formed through a dielectric layer may provide an electrical connection between an overlying structure (e.g., an interconnect line) and the source or drain region. The transistor may further comprise a gate stack having a capping layer over a metal.

Abstract translation: 在一个实施例中，晶体管包括在源极区域和漏极区域上的凸起结构。 升高的源结构可以包括选择性沉积的金属，例如选择性钨。 通过电介质层形成的自对准接触结构可以在上覆结构（例如，互连线）和源极或漏极区之间提供电连接。 晶体管还可以包括在金属上具有覆盖层的栅极堆叠。

公开(公告)号：US06841878B1

公开(公告)日：2005-01-11

申请号：US10672895

申请日：2003-09-26

Applicant: Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

Inventor： Mira Ben-Tzur ,  Krishnaswamy Ramkumar ,  Alain Blosse ,  Fuad Badrieh

IPC: H01L21/3205 ,  H01L21/768 ,  H01L23/48

CPC classification number: H01L21/32051 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/76838

Abstract: In one embodiment, a passivation level includes a low-k dielectric. The low-k dielectric helps lower the capacitance of a metal line in a last metal level, which may be just below the passivation level. In another embodiment, the metal line is relatively thick. This helps lower the metal line's resistance and resulting RC delay.

Abstract translation: 在一个实施例中，钝化层包括低k电介质。 低k电介质有助于降低金属线在最后一个金属电平的电容，这可能刚好低于钝化水平。 在另一个实施例中，金属线相对较厚。 这有助于降低金属线的电阻并导致RC延迟。

公开(公告)号：US06777307B1

公开(公告)日：2004-08-17

申请号：US10010833

申请日：2001-12-04

Applicant: Krishnaswamy Ramkumar ,  Steven S. Hedayati

Inventor： Krishnaswamy Ramkumar ,  Steven S. Hedayati

IPC: H01L2176

CPC classification number: H01L21/76229 ,  H01L21/3081 ,  H01L21/31053

Abstract: A method is provided which includes planarizing structures and/or layers such that step heights of reduced and more uniform thicknesses may be formed. In particular, a method is provided which includes polishing an upper layer of a topography to expose a first underlying layer and etching away remaining portions of the first underlying layer to expose a second underlying layer. The topography may then be subsequently planarized. As such, a method for fabricating shallow trench isolation regions may include forming one or more trenches extending through a stack arranged over a semiconductor substrate. Such a method may further include blanket depositing a dielectric over the trenches and the stack of layers such that the trenches are filled by the dielectric. The dielectric may then be planarized such that upper surfaces of the dielectric remaining within the trenches are coplanar with an upper surface of an adjacent layer of the stack.

Abstract translation: 提供了一种包括平坦化结构和/或层的方法，使得可以形成减小和更均匀厚度的台阶高度。 特别地，提供了一种方法，其包括抛光地形的上层以暴露第一下层并蚀刻掉第一下层的剩余部分以暴露第二下层。 随后可以将形貌平面化。 因此，用于制造浅沟槽隔离区域的方法可以包括形成延伸穿过布置在半导体衬底上的堆叠的一个或多个沟槽。 这种方法还可以包括在沟槽和层叠层上覆盖电介质，使得沟槽被电介质填充。 然后电介质可以被平坦化，使得保留在沟槽内的电介质的上表面与堆叠的相邻层的上表面共面。

公开(公告)号：US06436799B1

公开(公告)日：2002-08-20

申请号：US09670089

申请日：2000-09-26

Applicant: Krishnaswamy Ramkumar ,  Manuj Rathor

Inventor： Krishnaswamy Ramkumar ,  Manuj Rathor

IPC: H01L21425

CPC classification number: H01L29/518 ,  H01L21/28176 ,  H01L21/3003 ,  H01L21/324 ,  H01L29/517

Abstract: A method of making a semiconductor structure, includes annealing a structure in a deuterium-containing atmosphere. The structure includes (i) a substrate, (ii) a gate dielectric on the substrate, (iii) a gate on the gate dielectric, (iv) an etch-stop layer on the gate, and (v) an interlayer dielectric on the etch-stop layer.

公开(公告)号：US06399462B1

公开(公告)日：2002-06-04

申请号：US08885046

申请日：1997-06-30

Applicant: Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

Inventor： Krishnaswamy Ramkumar ,  Sang S. Kim ,  Sharmin Sadoughi ,  Pamela Trammel ,  Avner Shelem

IPC: H01L2176

CPC classification number: H01L21/7621

Abstract: A method of forming a field oxide or isolation region in a semiconductor die. A nitride layer (over an oxide layer disposed over a substrate) is patterned and subsequently etched so that the nitride layer has a nearly vertical sidewall. The oxide layer and the substrate in the isolation region are etched to form a recess in the substrate having a sloped surface with respect to the nearly vertical sidewall of the nitride layer. A field oxide is then grown in the recess using a high pressure, dry oxidizing atmosphere. The sloped sidewall of the substrate effectively moves the face of the exposed substrate away from the edge of the nitride layer sidewall. Compared to non-sloped techniques, the oxidation appears to start with a built-in offset from the patterned etch. This leads to a reduction of oxide encroachment and a nearly non-existent bird's beak. The desirable range of slopes for the substrate sidewall is approximately 50°-80° with respect to a nearly planar surface of the substrate in the recess.

Abstract translation: 一种在半导体管芯中形成场氧化物或隔离区域的方法。 对氮化物层（在衬底上方的氧化物层上方）进行构图并随后进行蚀刻，使得氮化物层具有几乎垂直的侧壁。 蚀刻隔离区域中的氧化物层和衬底，以在衬底中形成相对于氮化物层的几乎垂直侧壁具有倾斜表面的凹部。 然后使用高压，干燥的氧化气氛将场氧化物生长在凹陷中。 衬底的倾斜侧壁有效地将暴露的衬底的表面远离氮化物层侧壁的边缘移动。 与非倾斜技术相比，氧化似乎从图案化蚀刻的内置偏移开始。 这导致氧化物侵蚀的减少和几乎不存在的鸟的喙。 相对于凹部中的基板的几乎平坦的表面，衬底侧壁的期望的斜率范围大约为50°-80°。

公开(公告)号：US08691648B1

公开(公告)日：2014-04-08

申请号：US13168711

申请日：2011-06-24

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Soo Byun

IPC: H01L21/336

CPC classification number: H01L21/28282 ,  H01L29/66833 ,  H01L29/792

Abstract: Non-volatile semiconductor memories and methods of fabricating the same to improve performance thereof are provided. In one embodiment, the method includes: (i) forming a gate for a non-volatile memory transistor on a surface of a substrate overlaying a channel region formed therein, the gate including a charge trapping layer; and (ii) forming a strain inducing structure over the gate of the non-volatile memory transistor to increase charge retention of the charge trapping layer. Preferably, the memory transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) transistor comprising a SONOS gate stack. More preferably, the memory also includes a logic transistor on the substrate, and the step of forming a strain inducing structure comprises the step of forming the strain inducing structure over the logic transistor. Other embodiments are also disclosed.

Abstract translation: 提供非易失性半导体存储器及其制造方法以改善其性能。 在一个实施例中，该方法包括：（i）在覆盖其中形成的沟道区的衬底的表面上形成用于非易失性存储晶体管的栅极，栅极包括电荷俘获层; 和（ii）在非易失性存储晶体管的栅极上形成应变诱导结构，以增加电荷俘获层的电荷保留。 优选地，存储晶体管是包括SONOS栅极堆叠的氧化硅 - 氧化物 - 氮化物 - 氧化物 - 硅（SONOS）晶体管。 更优选地，存储器还包括在衬底上的逻辑晶体管，并且形成应变诱导结构的步骤包括在逻辑晶体管上形成应变诱导结构的步骤。 还公开了其他实施例。