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    Processing device with nonvolatile logic array backup
    84.
    发明授权
    Processing device with nonvolatile logic array backup 有权

    公开(公告)号：US10102889B2

    公开(公告)日：2018-10-16

    申请号：US13770304

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G11C7/22 ,  G06F3/06 ,  H03K3/3562 ,  G06F12/02 ,  G06F9/4401 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10 ,  G11C14/00

    Abstract: A processing device is operated using a plurality of volatile storage elements. N groups of M volatile storage elements of the plurality of volatile storage elements per group are connected to an N by M size non-volatile logic element array of a plurality of non-volatile logic element arrays using a multiplexer. The multiplexer connects one of the N groups to the N by M size non-volatile logic element array to store data from the M volatile storage elements into a row of the N by M size non-volatile logic element array at one time or to write data to the M volatile storage elements from a row of the N by M size non-volatile logic element array at one time. A corresponding non-volatile logic controller controls the multiplexer operation with respect to the connections between volatile storage elements and non-volatile storage elements.

    Nonvolatile logic array and power domain segmentation in processing device
    87.
    发明授权
    Nonvolatile logic array and power domain segmentation in processing device 有权
    非易失性逻辑阵列和功率域分割处理器件

    公开(公告)号：US09342259B2

    公开(公告)日：2016-05-17

    申请号：US13770498

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F1/00 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14 ,  G06F11/10

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A computing device includes a first set of non-volatile logic element arrays associated with a first function and a second set of non-volatile logic element arrays associated with a second function. The first and second sets of non-volatile logic element arrays are independently controllable. A first power domain supplies power to switched logic elements of the computing device, a second power domain supplies power to logic elements configured to control signals for storing data to or reading data from non-volatile logic element arrays, and a third power domain supplies power for the non-volatile logic element arrays. The different power domains are independently powered up or down based on a system state to reduce power lost to excess logic switching and the accompanying parasitic power consumption during the recovery of system state and to reduce power leakage to backup storage elements during regular operation of the computing device.

    Abstract translation: 计算设备包括与第一功能相关联的第一组非易失性逻辑元件阵列和与第二功能相关联的第二组非易失性逻辑元件阵列。 第一组和第二组非易失性逻辑元件阵列是独立可控的。 第一电源域向计算设备的交换逻辑元件供电，第二电源域为配置成控制用于将数据存储到非易失性逻辑单元阵列或从非易失性逻辑单元阵列读取数据的信号的逻辑元件供电，而第三电源域供电 用于非易失性逻辑元件阵列。 基于系统状态，不同的电源域被独立上电或下电，以减少在冗余逻辑切换期间的功率损耗以及在恢复系统状态期间伴随的寄生功率消耗，并且在计算的常规操作期间减少备用存储元件的功率泄漏 设备。

    Dual-port positive level sensitive reset data retention latch
    88.
    发明授权
    Dual-port positive level sensitive reset data retention latch 有权
    双端口正电平敏感复位数据保持锁存器

    公开(公告)号：US09270257B2

    公开(公告)日：2016-02-23

    申请号：US14454971

    申请日：2014-08-08

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Bartling ,  Sudhanshu Khanna

    IPC: H03K3/00 ,  H03K3/012 ,  H03K3/356

    CPC classification number: H03K3/356008

    Abstract: In an embodiment of the invention, a dual-port positive level sensitive reset data retention latch contains a clocked inverter and a dual-port latch. Data is clocked through the clocked inverter when clock signal CKT goes high, CLKZ goes low, reset control signal REN is high and retention control signal RET is low. The dual-port latch is configured to receive the output of the clocked inverter, a second data bit D2, the clock signals CKT and CLN, the retain control signals RET, the reset control signal REN and the control signals SS and SSN. The signals CKT, CLKZ, RET, REN, SS and SSN determine whether the output of the clocked inverter or the second data bit D2 is latched in the dual-port latch. Control signal RET determines when data is stored in the dual-port latch during retention mode.

    Abstract translation: 在本发明的实施例中，双端口正电平敏感复位数据保持锁存器包括时钟反相器和双端口锁存器。 当时钟信号CKT变高，CLKZ变为低电平，复位控制信号REN为高电平，保持控制信号RET为低电平时，数据通过时钟反相器进行时钟控制。 双端口锁存器被配置为接收时钟反相器的输出，第二数据位D2，时钟信号CKT和CLN，保持控制信号RET，复位控制信号REN和控制信号SS和SSN。 信号CKT，CLKZ，RET，REN，SS和SSN确定时钟反相器或第二数据位D2的输出是否锁存在双端口锁存器中。 在保持模式期间，控制信号RET确定数据何时存储在双端口锁存器中。

    Positive edge flip-flop with dual-port slave latch
    89.
    发明授权
    Positive edge flip-flop with dual-port slave latch 有权
    具有双端口从锁存器的正沿触发器

    公开(公告)号：US09083328B2

    公开(公告)日：2015-07-14

    申请号：US14457251

    申请日：2014-08-12

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Bartling ,  Sudhanshu Khanna

    IPC: H03K3/289 ,  H03K3/3562 ,  G01R31/3185 ,  H03K3/012

    CPC classification number: H03K3/3562 ,  G01R31/318541 ,  H03K3/012 ,  H03K3/35625

    Abstract: In an embodiment of the invention, a flip-flop circuit contains a first inverter, a pass gate, master latch, a transfer gate and a slave latch. The clock signals and retention control signals determine when the master latch is latched. The slave latch is configured to receive the output of the master latch, a second data bit D2, the clock signals, the retain control signals, the slave control signals. The clock signals, the retain control signals, and the slave control signals determine whether the output of the master latch or the second data bit D2 is latched in the slave latch. The retain control signals determine when data is stored in the slave latch during retention mode.

    Abstract translation: 在本发明的实施例中，触发器电路包含第一反相器，通孔，主锁存器，传输门和从锁存器。 时钟信号和保持控制信号确定主锁存器何时被锁存。 从锁存器被配置为接收主锁存器的输出，第二数据位D2，时钟信号，保持控制信号，从控制信号。 时钟信号，保持控制信号和从控制信号确定主锁存器或第二数据位D2的输出是否锁存在从锁存器中。 保留控制信号确定在保持模式期间数据何时存储在从锁存器中。

    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup
    90.
    发明授权
    Nonvolatile logic array with retention flip flops to reduce switching power during wakeup 有权
    具有保持触发器的非易失性逻辑阵列，以降低唤醒期间的开关电源

    公开(公告)号：US09058126B2

    公开(公告)日：2015-06-16

    申请号：US13770368

    申请日：2013-02-19

    Applicant: Texas Instruments Incorporated

    Inventor： Steven Craig Bartling ,  Sudhanshu Khanna

    IPC: G06F12/10 ,  G06F3/06 ,  G06F12/02 ,  G06F9/44 ,  G06F1/32 ,  G06F13/00 ,  G06F11/14

    CPC classification number: G11C7/22 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3275 ,  G06F1/3287 ,  G06F3/0679 ,  G06F3/0688 ,  G06F9/4401 ,  G06F9/4406 ,  G06F11/1032 ,  G06F11/1438 ,  G06F11/1469 ,  G06F12/0238 ,  G06F13/00 ,  G11C14/00 ,  H03K3/3562 ,  Y02D10/17 ,  Y02D10/171 ,  Y02D50/20

    Abstract: A processing device is operated using a plurality of volatile storage elements. Data in the plurality of volatile storage elements is stored in a plurality of non-volatile logic element arrays. A primary logic circuit portion of individual ones of the plurality of volatile storage elements is powered by a first power domain, and a slave stage circuit portion of individual ones of the plurality of volatile storage elements is powered by a second power domain. During a write back of data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements, the first power domain is powered down and the second power domain is maintained. In a further approach, the plurality of non-volatile logic element arrays is powered by a third power domain, which is powered down during regular operation of the processing device.

    Abstract translation: 使用多个易失性存储元件来操作处理装置。 多个易失性存储元件中的数据被存储在多个非易失性逻辑元件阵列中。 多个易失性存储元件中的各个易失性存储元件的主要逻辑电路部分由第一电源域供电，并且多个易失性存储元件中的单个的易失性存储元件的从属级电路部分由第二电源域供电。 在从多个非易失性逻辑单元阵列向多个易失性存储元件的数据写回期间，第一功率域被断电并维持第二功率域。 在另一种方法中，多个非易失性逻辑单元阵列由第三功率域供电，该第三功率域在处理设备的常规操作期间被关断。

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