公开(公告)号：US10755964B1

公开(公告)日：2020-08-25

申请号：US16427594

申请日：2019-05-31

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Lin-Yu Huang ,  Sheng-Tsung Wang ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L21/762 ,  H01L27/088 ,  H01L21/311

Abstract: A method and structure directed to providing a source/drain isolation structure includes providing a device having a first source/drain region adjacent to a second source/drain region. A masking layer is deposited between the first and second source/drain regions and over an exposed first part of the second source/drain region. After depositing the masking layer, a first portion of an ILD layer disposed on either side of the masking layer is etched, without substantial etching of the masking layer, to expose a second part of the second source/drain region and to expose the first source/drain region. After etching the first portion of the ILD layer, the masking layer is etched to form an L-shaped masking layer. After forming the L-shaped masking layer, a first metal layer is formed over the exposed first source/drain region and a second metal layer is formed over the exposed second part of the second source/drain region.

公开(公告)号：US20200161439A1

公开(公告)日：2020-05-21

申请号：US16406154

申请日：2019-05-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Jia-Chuan You ,  Chia-Hao Chang ,  Tien-Lu Lin ,  Yu-Ming Lin ,  Chih-Hao Wang

IPC: H01L29/417 ,  H01L29/66 ,  H01L29/78

Abstract: Semiconductor devices and methods of forming the same are provided. In one embodiment, a semiconductor device according to the present disclosure includes a fin extending from a substrate, a gate structure over a channel region of the fin, a source/drain contact over a source/drain region of the fin, a gate cut feature adjacent the gate structure, a source/drain contact isolation feature adjacent the source/drain contact, a spacer extending along a sidewall of the gate cut feature and a sidewall of the gate structure, a liner extending along a sidewall of the source/drain contact isolation feature and a sidewall of the source/drain contact; and an air gap sandwiched between the spacer and the liner. The gate cut feature and the source/drain contact isolation feature are separated by the spacer, the air gap and the liner.

公开(公告)号：US20190252319A1

公开(公告)日：2019-08-15

申请号：US16394483

申请日：2019-04-25

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76804 ,  H01L21/76807 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5221 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2221/1063 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first metal wire arranged within an inter-level dielectric (ILD) layer over a substrate and laterally separated in a first direction from a first closest air-gap by a first distance. A second metal wire is arranged within the ILD layer and is laterally separated in the first direction from a second closest air-gap by a second distance that is larger than the first distance. A via is disposed on an upper surface of the second metal wire.

公开(公告)号：US10276498B2

公开(公告)日：2019-04-30

申请号：US15853021

申请日：2017-12-22

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Cheng-Chi Chuang ,  Yung-Chih Wang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768 ,  H01L23/522

Abstract: In some embodiments, the present disclosure relates to an interconnect structure. The interconnect structure has a first dielectric layer disposed over a substrate and a conductive structure arranged within the first dielectric layer. An air-gap separates sidewalls of the conductive structure from the first dielectric layer. The air-gap continuously extends from a first side of the conductive structure to an opposing second side of the conductive structure.

公开(公告)号：US10074607B2

公开(公告)日：2018-09-11

申请号：US15016866

申请日：2016-02-05

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Tien-I Bao ,  Tien-Lu Lin ,  Wei-Chen Chu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/48 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76877 ,  H01L21/76885 ,  H01L21/76892 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/53276

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and an interconnect structure formed over the substrate. The interconnect structure includes a first dielectric layer formed over the substrate, and a first graphene layer formed in and on the first dielectric layer. The first graphene layer includes a first portion in the first dielectric layer and a second portion on the first dielectric layer and a first insulating layer formed over the first portion of the first graphene layer.

公开(公告)号：US20180090439A1

公开(公告)日：2018-03-29

申请号：US15819280

申请日：2017-11-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L21/768

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure, in some embodiments, relates to an integrated chip having a back-end-of-the-line interconnect stack. The integrated chip has a dielectric structure arranged over a substrate. A first interconnect structure is arranged within the dielectric structure and has sidewalls and a horizontally extending surface that define a recess within a lower surface of the first interconnect structure facing the substrate. A lower interconnect structure is arranged within the dielectric structure and extends from within the recess to a location between the first interconnect structure and the substrate. The first interconnect structure and the lower interconnect structure comprise one or more different conductive materials.

公开(公告)号：US20170084646A1

公开(公告)日：2017-03-23

申请号：US15364955

申请日：2016-11-30

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/146

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: A method for manufacturing an image sensor with deep trench spacing isolation is provided. A trench is formed in a semiconductor substrate, around and between a plurality of pixel regions of the semiconductor substrate. A cap is formed using epitaxy to seal a gap between sidewalls of the trench. Pixel sensors corresponding to the plurality of pixel regions are formed over or within the corresponding pixel regions. An image sensor resulting from the method is also provided.

公开(公告)号：US20160163749A1

公开(公告)日：2016-06-09

申请号：US14564196

申请日：2014-12-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Tai-I Yang ,  Jung-I Lin ,  Ta-Chun Lin ,  Tien-Lu Lin ,  Chen-Jong Wang

IPC: H01L27/146

CPC classification number: H01L21/764 ,  H01L21/76224 ,  H01L21/76227 ,  H01L21/76289 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/823481 ,  H01L21/823878 ,  H01L27/0921 ,  H01L27/1203 ,  H01L27/14612 ,  H01L27/1463 ,  H01L27/14632 ,  H01L27/14643 ,  H01L27/14654 ,  H01L27/14689 ,  H01L29/945

Abstract: An image sensor employing deep trench spacing isolation is provided. A plurality of pixel sensors is arranged over or within a semiconductor substrate. A trench is arranged in the semiconductor substrate around and between adjacent ones of the plurality of pixel sensors, and the trench has a gap located between sidewalls of the trench. A cap is arranged over or within the trench at a position overlying the gap. The cap seals the gap within the trench. A method of manufacturing the image sensor is also provided.

Abstract translation: 提供了采用深沟槽间隔隔离的图像传感器。 多个像素传感器布置在半导体衬底之上或之内。 沟槽在多个像素传感器周围和相邻的像素传感器之间并且在半导体衬底中布置，并且沟槽在沟槽的侧壁之间具有间隙。 在覆盖间隙的位置处，在沟槽之上或之内布置盖。 盖子密封沟槽内的间隙。 还提供了一种制造图像传感器的方法。

公开(公告)号：US20160005691A1

公开(公告)日：2016-01-07

申请号：US14321890

申请日：2014-07-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Hsiang-Wei Liu ,  Tai-I Yang ,  Cheng-Chi Chuang ,  Tien-Lu Lin

IPC: H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L23/5283 ,  H01L21/76802 ,  H01L21/76838 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/53266 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: The present disclosure relates to a method of forming a BEOL metallization layer that uses different conductive materials (e.g., metals) to fill different size openings in an inter-level dielectric layer, and an associated apparatus. In some embodiments, the present disclosure relates to an integrated chip having a first plurality of metal interconnect structures disposed within a first BEOL metallization layer, which include a first conductive material. The integrated chip also has a second plurality of metal interconnect structures disposed within the first BEOL metallization layer at positions laterally separated from the first plurality of metal interconnect structures. The second plurality of metal interconnect structures have a second conductive material that is different than the first conductive material. By forming different metal interconnect structures on a same BEOL metallization layer using different conductive materials, gap-fill problems in narrow BEOL metal interconnect structures can be mitigated, thereby improving reliability of integrated chips.

Abstract translation: 本公开涉及一种形成使用不同导电材料（例如，金属）填充层间电介质层中的不同尺寸的开口的BEOL金属化层的方法以及相关联的装置。 在一些实施例中，本公开涉及一种具有设置在第一BEOL金属化层内的第一多个金属互连结构的集成芯片，其包括第一导电材料。 集成芯片还具有在与第一多个金属互连结构横向分离的位置处设置在第一BEOL金属化层内的第二多个金属互连结构。 第二多个金属互连结构具有与第一导电材料不同的第二导电材料。 通过使用不同的导电材料在相同的BEOL金属化层上形成不同的金属互连结构，可以减小窄BEOL金属互连结构中的间隙填充问题，从而提高集成芯片的可靠性。