Method for driving a non-volatile semiconductor memory
    83.
    发明授权
    Method for driving a non-volatile semiconductor memory 失效
    用于驱动非易失性半导体存储器的方法

    公开(公告)号:US5715196A

    公开(公告)日:1998-02-03

    申请号:US684178

    申请日:1996-07-19

    摘要: An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译: 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极,源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器,通过位线连接到列解码器,并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分,例如二极管,对于施加在其上的不同电压电平,具有不同的电压 - 电流特性。 由于这样的布置,可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误,并且可以降低功耗。

    Non-volatile semiconductor memory having an array of non-volatile memory
cells and method for driving the same
    84.
    发明授权
    Non-volatile semiconductor memory having an array of non-volatile memory cells and method for driving the same 失效
    具有非易失性存储单元阵列的非易失性半导体存储器及其驱动方法

    公开(公告)号:US5627779A

    公开(公告)日:1997-05-06

    申请号:US505638

    申请日:1995-07-21

    摘要: An array of non-volatile memory cells arranged in rows and columns is provided. Each memory cell is composed of a transistor made up of a gate, a source, and drain and a capacitance section. Each memory cell is connected to a row decoder through a wordline, to a column decoder through a bitline, and to a source decoder through a sourceline. Arranged in a path extending from a bitline to a sourceline through a transistor is an anisotropic resistance section, e.g., a diode, exhibiting different voltage-current characteristics for different levels of voltages applied thereacross. Because of such arrangement, leakage current occurring to a deselected memory cell in a reading operation can be reduced or can be eliminated. Read errors due to leakage current can be avoided and the power consumption can be reduced.

    摘要翻译: 提供了排列成行和列的非易失性存储单元阵列。 每个存储单元由由栅极,源极和漏极以及电容部分构成的晶体管构成。 每个存储单元通过字线连接到行解码器,通过位线连接到列解码器,并通过源线连接到源解码器。 在从位线延伸到源极线通过晶体管的路径中布置的是各向异性电阻部分,例如二极管,对于施加在其上的不同电压电平,具有不同的电压 - 电流特性。 由于这样的布置,可以减少或可以消除在读取操作中对取消选择的存储单元发生的泄漏电流。 可以避免由于泄漏电流而导致的读取错误,并且可以降低功耗。

    Semiconductor memory having internal test circuit
    86.
    发明授权
    Semiconductor memory having internal test circuit 失效
    具有内部测试电路的半导体存储器

    公开(公告)号:US5457696A

    公开(公告)日:1995-10-10

    申请号:US925159

    申请日:1992-08-06

    申请人: Toshiki Mori

    发明人: Toshiki Mori

    IPC分类号: G11C29/34 G11C29/38 G11C29/00

    CPC分类号: G11C29/38 G11C29/34

    摘要: A random access semiconductor memory having an array of memory cells is provided with an internal test circuit for testing the contents of rows of stored test pattern data which are read from the array in units of data rows, each read from an entire row of cells of the array. The test circuit can be based on a set of transistors which are respectively coupled to the bit lines of the cell array, for detecting coincidence between the states of all of the bits of a data row that is read out, or coincidence between the states of a predetermined set of the row bits.

    摘要翻译: 具有存储单元阵列的随机存取半导体存储器被提供有内部测试电路,用于测试从阵列以数据行为单位读出的存储的测试图形数据的行的内容,每个数据行从单行的单元读取 阵列。 测试电路可以基于一组晶体管,其分别耦合到单元阵列的位线,用于检测读出的数据行的所有位的状态之间的一致性,或者是 预定的行位集合。

    Video memory with write mask from vector or direct input
    87.
    发明授权
    Video memory with write mask from vector or direct input 失效
    具有写入掩码的视频存储器,从矢量或直接输入

    公开(公告)号:US5198804A

    公开(公告)日:1993-03-30

    申请号:US545782

    申请日:1990-06-29

    申请人: Toshiki Mori

    发明人: Toshiki Mori

    摘要: A video memory includes a data storage section having a predetermined bit width of data writing and reading. A data input terminal has a predetermined bit width and is subjected to input data which represents at least a write start position and a write end position. Mask data are generated on the basis of the write start position and the write end position represented by input data. The mask data are fed to the data storage section. Write data are generated. The write data are fed to the data storage section. The bit width of data writing and reading of the data storage section is greater than the bit width of the data input terminal.