公开(公告)号：US08516335B2

公开(公告)日：2013-08-20

申请号：US12743454

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03M13/00

CPC分类号： H03M13/1165 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/27 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071 ,  H04L27/3416 ,  H04L27/3488 ,  H04L2001/0093

摘要： The present invention relates to a data processing apparatus and a data processing method which can improve the tolerance to errors of code bits of an LDPC code such as burst errors or erasure.Where one symbol is formed from two or more code bits of an LDPC (Low Density Parity Check) code, a column twist interleaver 24 carries out a re-arrangement process of re-arranging the code bits of the LDPC code such that a plurality of code bits corresponding to the value 1 included in one arbitrary row of a parity check matrix are not mapped to one symbol. The present invention can be applied, for example, to a transmission apparatus which transmits an LDPC code.

摘要翻译： 本发明涉及一种数据处理装置和数据处理方法，其可以提高诸如突发错误或擦除之类的LDPC码的码位的容错。 在一个符号由LDPC（低密度奇偶校验）码的两个或多个码位形成的情况下，列扭曲交织器24执行重新排列LDPC码的码位的重新布置处理，使得多个 对应于包括在奇偶校验矩阵的一个任意行中的值1的码位不映射到一个符号。 本发明可以应用于例如发送LDPC码的发送装置。

公开(公告)号：USRE44420E1

公开(公告)日：2013-08-06

申请号：US12611227

申请日：2004-04-19

申请人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro Iida

发明人： Takashi Yokokawa ,  Toshiyuki Miyauchi ,  Yasuhiro Iida

IPC分类号： H03M13/00

CPC分类号： H03M13/1168 ,  H03M13/11 ,  H03M13/1114 ,  H03M13/1134 ,  H03M13/1137 ,  H03M13/1145 ,  H03M13/1188 ,  H03M13/6505 ,  H03M13/6566 ,  H03M13/6577

摘要： The present invention relates to a decoding apparatus and a decoding method for realizing the decoding of LDPC codes, in which, while the circuit scale is suppressed, the operating frequency can be suppressed within a sufficiently feasible range, and control of memory access can be performed easily, and to a program therefor. A check matrix of LDPC codes is formed by a combination of a (P×P) unit matrix, a matrix in which one to several 1s of the unit matrix are substituted with 0, a matrix in which they are cyclically shifted, a matrix, which is the sum of two or more of them, and a (P×P) 0-matrix. A check node calculator 313 simultaneously performs p check node calculations. A variable node calculator 319 simultaneously performs p variable node calculations.

摘要翻译： 本发明涉及一种用于实现LDPC码的解码的解码装置和解码方法，其中在抑制电路规模的同时，可以在足够可行的范围内抑制工作频率，并且可以执行存储器访问的控制 很容易，也是一个程序。 LDPC码的校验矩阵通过（P×P）单位矩阵，单位矩阵中的1至数个1被0替换的矩阵，循环移位的矩阵，矩阵， 它们是两个或更多个的和，（P×P）0矩阵的和。 校验节点计算器313同时执行p校验节点计算。 变量节点计算器319同时执行p变量节点计算。

公开(公告)号：US08489956B2

公开(公告)日：2013-07-16

申请号：US12743720

申请日：2008-11-26

申请人： Takashi Yokokawa ,  Makiko Yamamoto

发明人： Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： G06F11/00

CPC分类号： H03M13/1165 ,  H03M13/1137 ,  H03M13/1185 ,  H03M13/255 ,  H03M13/2703 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/6552 ,  H04L1/0057 ,  H04L1/0071

摘要： The present invention relates to a data processing apparatus and a data processing apparatus which can improve the tolerance to an error of a code bit of an LDPC code such as burst errors or erasure. An LDPC encoding section 21 carries out LDPC encoding in accordance with a parity check matrix in which a parity matrix which is a portion corresponding to parity bits of an LDPC (Low Density Parity Check) code has a staircase structure, and outputs an LDPC code. A parity interleaver 23 carries out parity interleave of interleaving the parity bits of the LDPC code outputted from the LDPC encoding section 21 to the positions of other parity bits. The present invention can be applied, for example, to a transmission apparatus which transmits an LDPC code.

摘要翻译： 数据处理装置和数据处理装置技术领域本发明涉及一种数据处理装置和数据处理装置，其可以提高对诸如突发错误或擦除的LDPC码的码位的误差的容限。 LDPC编码部分21根据奇偶校验矩阵执行LDPC编码，其中作为与LDPC（低密度奇偶校验）码的奇偶校验位对应的部分的奇偶校验矩阵具有阶梯结构，并输出LDPC码。 奇偶交织器23执行将从LDPC编码部分21输出的LDPC码的奇偶校验位交织到其他奇偶校验位的位置的奇偶交织。 本发明可以应用于例如发送LDPC码的发送装置。

公开(公告)号：US08488695B2

公开(公告)日：2013-07-16

申请号：US12958912

申请日：2010-12-02

申请人： Takashi Yokokawa ,  Tadaaki Yuba ,  Hidetoshi Kawauchi ,  Hitoshi Sakai ,  Yuken Goto ,  Suguru Houchi

发明人： Takashi Yokokawa ,  Tadaaki Yuba ,  Hidetoshi Kawauchi ,  Hitoshi Sakai ,  Yuken Goto ,  Suguru Houchi

IPC分类号： H04K1/10

CPC分类号： H04L25/02 ,  H04L25/0232 ,  H04L2025/03414

摘要： A receiving apparatus for receiving an orthogonal frequency division multiplexing (OFDM) signal including a frame having one frame length of a plurality of patterns. The apparatus comprises an acquiring section to acquire information regarding a preamble signal from an OFDM signal from a transmitting apparatus; a frame determining section to determine whether the one frame length is short in the frame based on the information regarding the acquired preamble signal; and a time interpolating section to obtain transmission path characteristics by comparing a pilot contained in the preamble signal with a known pilot corresponding to the pilot in a phase of transmission, when the frame determining section determines that the one frame length is short in the frame, and to interpolate a data portion in a time direction based on transmission path characteristics.

摘要翻译： 一种用于接收正交频分多路复用（OFDM）信号的接收装置，包括具有多个模式的一帧长度的帧。 该装置包括：获取部分，从发送装置获取来自OFDM信号的关于前导码信号的信息; 帧确定部分，用于基于关于所获取的前导信号的信息来确定帧中的一个帧长度是否短; 以及时间内插部分，当帧确定部分确定帧中的一个帧长度短时，通过将包含在前导码信号中的导频与对应于传输的相位中的导频的已知导频进行比较来获得传输路径特性， 并且基于传输路径特性在时间方向上内插数据部分。

公开(公告)号：US08448049B2

公开(公告)日：2013-05-21

申请号：US12783883

申请日：2010-05-20

申请人： Lui Sakai ,  Takashi Yokokawa

发明人： Lui Sakai ,  Takashi Yokokawa

IPC分类号： H03M13/00

CPC分类号： H03M13/116 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/1185 ,  H03M13/15 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/2945 ,  H03M13/356 ,  H03M13/616 ,  H03M13/6356 ,  H03M13/6362 ,  H03M13/6552 ,  H03M13/6555 ,  H04L1/0057 ,  H04L1/0065 ,  H04L1/0068 ,  H04L1/0071 ,  H04L27/2602

摘要： Disclosed herein is a receiving apparatus including a reception device configured to receive a code sequence coded in LDPC (Low Density Parity Check) and punctured at least partially as a target to be decoded; and an LDPC decoding device configured to perform a punctured matrix transform process including a first and a second process on an original parity check matrix noted to have punctured bits or symbols and used in the LDPC coding. The LDPC decoding device further performs the first process to carry out Galois field addition operations on those rows of the original parity check matrix to set the non-zero elements to zero. The LDPC decoding device further performs the second process to delete the columns rid of the non-zero elements. The LDPC decoding device uses the matrix resulting from the process as the parity check matrix for performing an LDPC decoding process on the code sequence.

摘要翻译： 这里公开了一种接收装置，包括：接收装置，被配置为接收以LDPC（低密度奇偶校验）编码的码序列，并至少部分地作为要解码的目标进行穿孔; 以及LDPC解码装置，被配置为执行包括第一和第二处理的穿孔矩阵变换处理，所述原始奇偶校验矩阵被标记为具有穿孔比特或符号并用于LDPC编码。 LDPC解码装置还执行对原始奇偶校验矩阵的那些行执行伽罗瓦域加法运算的第一处理，以将非零元素设置为零。 LDPC解码装置还执行第二处理以删除非零元素的列。 LDPC解码装置使用由该处理得到的矩阵作为用于对码序列进行LDPC解码处理的奇偶校验矩阵。

公开(公告)号：US08437426B2

公开(公告)日：2013-05-07

申请号：US12567856

申请日：2009-09-28

申请人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

发明人： Hidetoshi Kawauchi ,  Masayuki Hattori ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Kazuhiro Shimizu ,  Kazuhisa Funamoto

IPC分类号： H04B1/38 ,  H04N7/12 ,  H04L27/00

CPC分类号： H04L27/2662 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2656 ,  H04L27/2665

摘要： Disclosed herein is a receiving apparatus including: first to third position determination sections configured to determine the start position of an FFT interval which serves as a signal interval targeted for FFT by an FFT section; a selection section configured to select one of those start positions of the FFT interval which are determined by the first through the third position determination section; and the FFT section configured to perform FFT on the OFDM time domain signal by regarding the start position selected by the selection section as the start position of the FFT interval in order to generate the first OFDM frequency domain signal.

摘要翻译： 本发明公开了一种接收装置，包括：第一至第三位置确定部分，被配置为确定FFT间隔的起始位置，其作为由FFT部分进行FFT的信号间隔; 选择部，被配置为选择由所述第一至第三位置确定部确定的所述FFT间隔的那些起始位置之一; FFT部，被配置为通过将由选择部选择出的开始位置作为FFT间隔的开始位置，对OFDM时域信号进行FFT，以生成第一OFDM频域信号。

公开(公告)号：US08363755B2

公开(公告)日：2013-01-29

申请号：US12788398

申请日：2010-05-27

申请人： Suguru Houchi ,  Naoki Yoshimochi ,  Takuya Okamoto ,  Yuken Goto ,  Takashi Yokokawa

发明人： Suguru Houchi ,  Naoki Yoshimochi ,  Takuya Okamoto ,  Yuken Goto ,  Takashi Yokokawa

IPC分类号： H04L27/00

CPC分类号： H04L27/2662 ,  H04L5/0023 ,  H04L5/0048 ,  H04L25/0204 ,  H04L25/0226 ,  H04L25/0232 ,  H04L25/03159 ,  H04L27/2649 ,  H04L27/2675 ,  H04L2025/03414 ,  H04L2025/03426

摘要： A signal receiving apparatus includes: an acquisition section configured to acquire an Orthogonal Frequency Division Multiplexing signal resulting from combination of a plurality of signals transmitted by a plurality of signal transmitting apparatus by adoption of an Orthogonal Frequency Division Multiplexing method; and a demodulation section configured to carry out partial processing of processing to demodulate the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section by making use of either first pilot signals or second pilot signals where the first pilot signals are pilot signals extracted from the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section as signals having the same phase for all the signal transmitting apparatus, and the second pilot signals are pilot signals extracted from the Orthogonal Frequency Division Multiplexing signal acquired by the acquisition section as signals having different phases depending on the signal transmitting apparatus.

摘要翻译： 信号接收装置包括：获取部，被配置为通过采用正交频分复用方法获取由多个信号发送装置发送的多个信号的组合而得到的正交频分复用信号; 以及解调部，被配置为执行处理的部分处理，以通过利用第一导频信号或第二导频信号来解调由获取部获取的正交频分复用信号，其中第一导频信号是从正交频率提取的导频信号 由采集部分获取的分复用信号作为对于所有信号发送装置具有相同相位的信号，并且第二导频信号是从由采集部分获取的正交频分复用信号中提取的导频信号，作为具有不同相位的信号，取决于 信号发送装置。

公开(公告)号：US08281205B2

公开(公告)日：2012-10-02

申请号：US12252470

申请日：2008-10-16

申请人： Takashi Yokokawa

发明人： Takashi Yokokawa

IPC分类号： H03M13/00

CPC分类号： H03M13/1168 ,  H03M13/1111 ,  H03M13/1137 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/616 ,  H03M13/6508 ,  H03M13/6577

摘要： Disclosed herein is a decoding apparatus for decoding an LDPC code, the decoding apparatus including: a message computation section configured to carry out a process of decoding received values, where notation F denotes a non-unity measure of the integer P, and outputting F messages; a shift section configured to carry out F×F cyclic shift operations on the F messages and output F messages; a storage section configured to store the F messages and allow the stored F messages to be read out or to store F received values cited above and allow the stored F received values to be read out; and a control section configured to control an operation to supply a unit composed of the F received values to the message computation section by carrying out at least a column rearrangement process or a process equivalent to the column rearrangement process on the received values.

摘要翻译： 这里公开了一种解码LDPC码的解码装置，该解码装置包括：消息计算部，被配置为执行对接收值进行解码的处理，其中，F表示整数P的非一致性度量，并输出F个消息 ; 移位部，被配置为对所述F个消息进行F×F循环移位操作，并输出F个消息; 存储部，其被配置为存储所述F个消息，并且允许所存储的F个消息被读出或存储上述引用的F个接收值，并且允许读取所存储的F个接收值; 以及控制部，被配置为通过对接收到的值执行至少一个列重排处理或与该列重排处理相当的处理来控制将由F个接收值组成的单元提供给消息计算部的操作。

公开(公告)号：US08179955B2

公开(公告)日：2012-05-15

申请号：US12260327

申请日：2008-10-29

申请人： Matthew Paul Athol Taylor ,  Samuel Asanbeng Atungsiri ,  Takashi Yokokawa ,  Makiko Yamamoto

发明人： Matthew Paul Athol Taylor ,  Samuel Asanbeng Atungsiri ,  Takashi Yokokawa ,  Makiko Yamamoto

IPC分类号： H03H7/30

CPC分类号： H03M13/1168 ,  H03M13/1137 ,  H03M13/1148 ,  H03M13/116 ,  H03M13/1165 ,  H03M13/1185 ,  H03M13/15 ,  H03M13/152 ,  H03M13/255 ,  H03M13/2707 ,  H03M13/271 ,  H03M13/2906 ,  H04L1/0057 ,  H04L1/0071 ,  H04L5/0007 ,  H04L5/0044 ,  H04L5/0064 ,  H04L27/2626 ,  H04L27/2647 ,  H04L27/34

摘要： A data processing apparatus communicates data bits on a predetermined number of sub-carrier signals of an Orthogonal Frequency Division Multiplexed (OFDM) symbol. The data processing apparatus comprises a parity interleaver operable to perform parity interleaving on Low Density Parity Check (LDPC) encoded data bits obtained by performing LDPC encoding according to a parity check matrix of an LDPC code including a parity matrix corresponding to parity bits of the LDPC code, the parity matrix having a stepwise structure, so that a parity bit of the LDPC encoded data bits is interleaved to a different parity bit position. A mapping unit maps the parity interleaved bits onto data symbols corresponding to modulation symbols of a modulation scheme of the OFDM sub-carrier signals.

摘要翻译： 数据处理装置在正交频分复用（OFDM）符号的预定数量的副载波信号上传送数据位。 数据处理装置包括奇偶校验交织器，其可操作以对通过执行LDPC编码而获得的低密度奇偶校验（LDPC）编码数据比特进行奇偶校验交织，所述LDPC编码数据比特根据LDPC码的奇偶校验矩阵，该LDPC码包括与LDPC码奇偶校验位对应的奇偶校验矩阵 代码，奇偶校验矩阵具有逐步结构，使得LDPC编码数据位的奇偶校验位被交织到不同的奇偶校验位位置。 映射单元将奇偶交织的比特映射到对应于OFDM子载波信号的调制方案的调制符号的数据符号上。

公开(公告)号：US08045945B2

公开(公告)日：2011-10-25

申请号：US12393093

申请日：2009-02-26

申请人： Hidetoshi Kawauchi ,  Tadaaki Yuba ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Takuya Okamoto ,  Tamotsu Ikeda ,  Koji Naniwada ,  Kazuhiro Shimizu ,  Lachlan Bruce Michael

发明人： Hidetoshi Kawauchi ,  Tadaaki Yuba ,  Toshiyuki Miyauchi ,  Takashi Yokokawa ,  Takuya Okamoto ,  Tamotsu Ikeda ,  Koji Naniwada ,  Kazuhiro Shimizu ,  Lachlan Bruce Michael

IPC分类号： H04B1/10

CPC分类号： H04B1/1036 ,  H04L5/0048 ,  H04L25/0216 ,  H04L25/0232

摘要： A reception apparatus including an extraction section; a transmission line characteristic estimation section; an interpolation section; a compensation section; a detection section; and a selection section.

摘要翻译： 一种接收装置，包括提取部分; 传输线特性估计部; 插值部分; 赔偿部分; 检测部; 和选择部分。