公开(公告)号：US07598545B2

公开(公告)日：2009-10-06

申请号：US11111592

申请日：2005-04-21

申请人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

发明人： Eduard A. Cartier ,  Matthew W. Copel ,  Bruce B. Doris ,  Rajarao Jammy ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Keith Kwong Hon Wong

IPC分类号： H01L29/00

CPC分类号： H01L21/823842

摘要： The present invention is directed to CMOS structures that include at least one nMOS device located on one region of a semiconductor substrate; and at least one pMOS device located on another region of the semiconductor substrate. In accordance with the present invention, the at least one nMOS device includes a gate stack comprising a gate dielectric, a low workfunction elemental metal having a workfunction of less than 4.2 eV, an in-situ metallic capping layer, and a polysilicon encapsulation layer and the at least one pMOS includes a gate stack comprising a gate dielectric, a high workfunction elemental metal having a workfunction of greater than 4.9 eV, a metallic capping layer, and a polysilicon encapsulation layer. The present invention also provides methods of fabricating such a CMOS structure.

摘要翻译： 本发明涉及包括位于半导体衬底的一个区域上的至少一个nMOS器件的CMOS结构; 以及位于半导体衬底的另一区域上的至少一个pMOS器件。 根据本发明，所述至少一个nMOS器件包括栅极堆叠，其包括栅极电介质，功函数小于4.2eV的低功函数元素金属，原位金属覆盖层和多晶硅封装层，以及 所述至少一个pMOS包括包括栅极电介质的栅极堆叠，具有大于4.9eV的功函数的高功函数元素金属，金属覆盖层和多晶硅封装层。 本发明还提供了制造这种CMOS结构的方法。

公开(公告)号：US07569466B2

公开(公告)日：2009-08-04

申请号：US11303715

申请日：2005-12-16

申请人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

发明人： Alessandro C. Callegari ,  Michael P. Chudzik ,  Bruce B. Doris ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  Michelle L. Steen

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L21/823842

摘要： A semiconductor structure including at least one n-type field effect transistor (nFET) and at least one p-type field effect transistor (pFET) that both include a metal gate having nFET behavior and pFET behavior, respectively, without including an upper polysilicon gate electrode is provided. The present invention also provides a method of fabricating such a semiconductor structure.

摘要翻译： 包括至少一个n型场效应晶体管（nFET）和至少一个p型场效应晶体管（pFET）的半导体结构，其分别包括具有nFET行为的金属栅极和pFET行为，而不包括上多晶硅栅极 提供电极。 本发明还提供一种制造这种半导体结构的方法。

公开(公告)号：US20090181505A1

公开(公告)日：2009-07-16

申请号：US12013846

申请日：2008-01-14

申请人： Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

发明人： Takashi Ando ,  Eduard A. Cartier ,  Changhwan Choi ,  Elizabeth A. Duch ,  Bruce B. Doris ,  Young-Hee Kim ,  Vijay Narayanan ,  James Pan ,  Vamsi K. Paruchuri

IPC分类号： H01L21/8238

CPC分类号： H01L29/66545 ,  H01L21/28088 ,  H01L21/823842 ,  H01L21/823857 ,  H01L21/823871 ,  H01L27/1203 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665

摘要： In one embodiment, the invention is a method and apparatus for fabricating a high-performance band-edge complementary metal-oxide-semiconductor device. One embodiment of a method for fabricating a complementary metal-oxide-semiconductor device includes fabricating an n-type metal-oxide-semiconductor device using a gate first process, and fabricating a p-type metal-oxide-semiconductor device using a gate last process.

摘要翻译： 在一个实施例中，本发明是用于制造高性能带边互补金属氧化物半导体器件的方法和装置。 用于制造互补金属氧化物半导体器件的方法的一个实施例包括使用栅极第一工艺制造n型金属氧化物半导体器件，以及使用栅极最后工艺制造p型金属氧化物半导体器件 。

公开(公告)号：US20090065817A1

公开(公告)日：2009-03-12

申请号：US11852906

申请日：2007-09-10

申请人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

发明人： Eduard A. Cartier ,  Rashmi Jha ,  Sivananda Kanakasabapathy ,  Xi Li ,  Renee T. Mo ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark T. Robson ,  Kathryn T. Schonenberg ,  Michelle L. Steen ,  Richard Wise ,  Ying Zhang

IPC分类号： H01L21/311 ,  H01L29/78

CPC分类号： H01L21/31116 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.

摘要翻译： 本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。 本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。 该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在所述FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

公开(公告)号：US20090039436A1

公开(公告)日：2009-02-12

申请号：US11835320

申请日：2007-08-07

申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark Todhunter Robson ,  Michelle L. Steen ,  Ying Zhang

发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri ,  Mark Todhunter Robson ,  Michelle L. Steen ,  Ying Zhang

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： A CMOS structure is disclosed in which both type of FET devices have gate insulators containing high-k dielectrics, and gates containing metals. The threshold of the two type of devices are adjusted in separate manners. One type of device has its threshold set by exposing the high-k dielectric to oxygen. During the oxygen exposure the other type of device is covered by a stressing dielectric layer, which layer also prevents oxygen penetration to its high-k gate dielectric. The high performance of the CMOS structure is further enhanced by adjusting the effective workfunctions of the gates to near band-edge values both NFET and PFET devices.

摘要翻译： 公开了CMOS结构，其中两种类型的FET器件具有包含高k电介质的栅极绝缘体和包含金属的栅极。 两种类型的设备的阈值以不同的方式进行调整。 一种类型的器件通过将高k电介质暴露于氧气而设置其阈值。 在氧暴露期间，另一种类型的器件被应力介电层覆盖，该层还防止氧气渗透到其高k栅极电介质。 通过将栅极的有效功函数调整到NFET和PFET器件的近带边缘值，进一步增强了CMOS结构的高性能。

公开(公告)号：US20090039435A1

公开(公告)日：2009-02-12

申请号：US11835318

申请日：2007-08-07

申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L29/78 ,  H01L21/8238

CPC分类号： H01L21/823842 ,  H01L21/823807 ,  H01L29/49 ,  H01L29/513 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7843 ,  H01L29/785

摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators, metal containing gates, and threshold adjusting cap layers. The NFET gate stack and the PFET gate stack each has a portion which is identical in the NFET device and in the PFET device. This identical portion contains at least a gate metal layer and a cap layer. Due to the identical portion, device fabrication is simplified, requiring a reduced number of masks. Furthermore, as a consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted with each other in direct physical contact. Device thresholds are further adjusted by oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

公开(公告)号：US20090039434A1

公开(公告)日：2009-02-12

申请号：US11835310

申请日：2007-08-07

申请人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

发明人： Bruce B. Doris ,  Eduard Albert Cartier ,  Barry Paul Linder ,  Vijay Narayanan ,  Vamsi Paruchuri

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823857 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/7833 ,  H01L29/7843

摘要： FET device structures are disclosed with the PFET and NFET devices having high-k dielectric gate insulators and metal containing gates. The metal layers of the gates in both the NFET and PFET devices have been fabricated from a single common metal layer. Due to the single common metal, device fabrication is simplified, requiring a reduced number of masks. Also, as a further consequence of using a single layer of metal for the gates of both type of devices, the terminal electrodes of NFETs and PFETs can be butted to each other in direct physical contact. Device thresholds are adjusted by the choice of the common metal material and oxygen exposure of the high-k dielectric. Threshold values are aimed for low power consumption device operation.

摘要翻译： 公开了具有高k介质栅极绝缘体和含金属栅极的PFET和NFET器件的FET器件结构。 NFET和PFET器件中的栅极的金属层已经由单个公共金属层制造。 由于单个普通金属，器件制造简化，需要减少数量的掩模。 此外，作为使用单层金属作为两种类型的器件的栅极的进一步的结果，NFET和PFET的端子电极可以直接物理接触地彼此对接。 通过选择普通金属材料和高k电介质的氧气曝光来调节器件阈值。 阈值是针对低功耗设备操作的。

公开(公告)号：US20090008725A1

公开(公告)日：2009-01-08

申请号：US11773160

申请日：2007-07-03

申请人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

发明人： Supratik Guha ,  Fenton R. McFeely ,  Vijay Narayanan ,  Vamsi K. Paruchuri ,  John J. Yurkas

IPC分类号： H01L29/76 ,  H01L21/3205

CPC分类号： H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518

摘要： A method of forming an electropositive metal-containing capping layer atop a stack of a high k gate dielectric/interfacial layer that avoids chemically and physically altering the high k gate dielectric and the interfacial layer is provided. The method includes chemical vapor deposition of an electropositive metal-containing precursor at a temperature that is about 400° C. or less. The present invention also provides semiconductor structures such as, for example, MOSCAPs and MOSFETs, that include a chemical vapor deposited electropositive metal-containing capping layer atop a stack of a high k gate dielectric and an interfacial layer. The presence of the CVD electropositive metal-containing capping layer does not physically or chemically alter the high k gate dielectric and the interfacial layer.

公开(公告)号：US20090008720A1

公开(公告)日：2009-01-08

申请号：US12211649

申请日：2008-09-16

申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L29/423 ,  H01L27/092

CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.

公开(公告)号：US20090008719A1

公开(公告)日：2009-01-08

申请号：US12211647

申请日：2008-09-16

申请人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

发明人： Bruce B. Doris ,  Young-Hee Kim ,  Barry P. Linder ,  Vijay Narayanan ,  Vamsi K. Paruchuri

IPC分类号： H01L27/092 ,  H01L29/423

CPC分类号： H01L21/823857 ,  H01L21/823878 ,  H01L21/84

摘要： A complementary metal oxide semiconductor (CMOS) structure including at least one nFET and at least one pFET located on a surface of a semiconductor substrate is provided. In accordance with the present invention, the nFET and the pFET both include at least a single gate metal and the nFET gate stack is engineered to have a gate dielectric stack having no net negative charge and the pFET gate stack is engineered to have a gate dielectric stack having no net positive charge. In particularly, the present invention provides a CMOS structure in which the nFET gate stack is engineered to include a band edge workfunction and the pFET gate stack is engineered to have a ¼ gap workfunction. In one embodiment of the present invention, the first gate dielectric stack includes a first high k dielectric and an alkaline earth metal-containing layer or a rare earth metal-containing layer, while the second high k gate dielectric stack comprises a second high k dielectric.