公开(公告)号：US08810946B2

公开(公告)日：2014-08-19

申请号：US13641239

申请日：2011-03-28

申请人： Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

发明人： Kan Yasui ,  Harukazu Miyamoto ,  Masukazu Igarashi

IPC分类号： G11B5/127

CPC分类号： G11B5/3146 ,  G11B5/1278 ,  G11B5/3116 ,  G11B5/314 ,  G11B5/315 ,  G11B2005/0024

摘要： A microwave-assisted magnetic recording system configured to perform magnetic recording with high density, including a high-frequency magnetic field generation element whose width is narrower than a track width of a main pole. A magnetic field vector from the main pole is perpendicularly incident on a film surface of the high-frequency magnetic field generating unit, by a shield material arranged to have a high magnetic permeability so that the main pole magnetic field is corrected and induced, and a hard bias layer to which a desired static magnetic field is added. Areas having high magnetic field gradients overlap each other by performing an offset of the high-frequency magnetic field generating unit of the magnetic head from the central line of the main pole.

摘要翻译： 一种被配置为执行高密度磁记录的微波辅助磁记录系统，包括宽度窄于主极的轨道宽度的高频磁场产生元件。 来自主极的磁场矢量垂直入射在高频磁场产生单元的膜表面上，通过屏蔽材料被布置成具有高导磁率，使得主极磁场被校正和感应，并且 添加了期望的静磁场的硬偏压层。 通过从主极的中心线执行磁头的高频磁场产生单元的偏移，具有高磁场梯度的区域彼此重叠。

公开(公告)号：US08193053B2

公开(公告)日：2012-06-05

申请号：US12763402

申请日：2010-04-20

申请人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

发明人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

摘要翻译： 本发明的目的是提供一种可以高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。

公开(公告)号：US20100302688A1

公开(公告)日：2010-12-02

申请号：US12784405

申请日：2010-05-20

申请人： Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

发明人： Masato Shiimoto ,  Kan Yasui ,  Nobuo Yoshida ,  Hiroyuki Takazawa

IPC分类号： G11B5/127

CPC分类号： G11B5/3932 ,  B82Y25/00 ,  G01R33/093 ,  G01R33/098 ,  H01L43/08 ,  H01L43/10

摘要： According to one embodiment, a magnetoresistive effect head includes a lower magnetic shield provided on a substrate, a magnetoresistive effect film laminated from a pinned layer with a pinned direction of magnetization, an intermediate layer, a free layer having a varying direction of magnetization controlled by an applied external magnetic field, a magnetic domain control layer formed with an intervening insulation layer on both sides in a track width direction of the magnetoresistive effect film, an upper magnetic shield, and electrodes for directing sense current flow in a direction perpendicular to a film surface of the magnetoresistive effect film, wherein a magnetic field applied by the magnetic domain control layer to a region away from an ABS of the free layer is at least 1.4 times larger than a magnetic field applied by the magnetic domain control layer to a region near the ABS of the free layer.

摘要翻译： 根据一个实施例，磁阻效应头包括设置在基板上的下磁屏蔽，从具有钉扎方向的钉扎层层压的磁阻效应膜，中间层，具有变化的磁化方向的自由层， 施加的外部磁场，在磁阻效应膜的磁道宽度方向上在两侧形成有中间绝缘层的磁畴控制层，上磁屏蔽和用于引导垂直于膜的方向的感测电流的电极 磁阻效应膜的表面，其中由磁畴控制层施加到远离自由层的ABS的区域的磁场比由磁畴控制层施加到接近的区域的磁场的至少大1.4倍 ABS的自由层。

公开(公告)号：US20100135080A1

公开(公告)日：2010-06-03

申请号：US12648796

申请日：2009-12-29

申请人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： G11C16/04 ,  H01L29/792

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US07723779B2

公开(公告)日：2010-05-25

申请号：US11437610

申请日：2006-05-22

申请人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

发明人： Digh Hisamoto ,  Shin'ichiro Kimura ,  Daiske Okada ,  Kan Yasui

IPC分类号： H01L21/336

CPC分类号： H01L27/115 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/11568 ,  H01L29/792

摘要： An object of the present invention is to provide an integrated semiconductor nonvolatile storage device that can be read at high speed and reprogrammed an increased number of times.In the case of conventional nonvolatile semiconductor storage devices having a split-gate structure, there is a tradeoff between the read current and the maximum allowable number of reprogramming operations. To overcome this problem, an integrated semiconductor nonvolatile storage device of the present invention is configured such that memory cells having different memory gate lengths are integrated on the same chip. This allows the device to be read at high speed and reprogrammed an increased number of times.

摘要翻译： 本发明的目的是提供一种能够高速读取并重新编程次数增加的集成半导体非易失性存储装置。 在具有分割栅结构的常规非易失性半导体存储器件的情况下，读取电流和最大可允许重编程操作次数之间存在权衡。 为了克服这个问题，本发明的集成半导体非易失性存储装置被配置为使得具有不同存储器栅极长度的存储单元集成在同一芯片上。 这允许以高速读取设备并重新编程增加的次数。

公开(公告)号：US20100118448A1

公开(公告)日：2010-05-13

申请号：US12615221

申请日：2009-11-09

申请人： Kan Yasui ,  Masato Shiimoto ,  Takeshi Nakagawa ,  Hiroyuki Katada ,  Nobuo Yoshida ,  Hiroyuki Hoshiya

发明人： Kan Yasui ,  Masato Shiimoto ,  Takeshi Nakagawa ,  Hiroyuki Katada ,  Nobuo Yoshida ,  Hiroyuki Hoshiya

IPC分类号： G11B5/127

CPC分类号： G11B5/3163 ,  G11B5/398

摘要： In one embodiment, a differential-type magnetic read head includes a differential-type magneto-resistive-effect film formed on a substrate, and a pair of electrodes for applying current in a direction perpendicular to a film plane of the film. The film includes a first and second stacked film, each having a pinned layer, an intermediate layer, and a free layer, with the second stacked film being formed on the first stacked film. A side face in a track width direction of the film is shaped to have an inflection point at an intermediate position in a thickness direction of the film, and the side face is shaped to be approximately vertical to the substrate in an upward direction of the substrate from the inflection point. Also, the side face is shaped to be gradually increased in track width as approaching the substrate in a downward direction of the substrate from the inflection point.

摘要翻译： 在一个实施例中，差分型磁读头包括形成在基板上的差分型磁阻效应膜和用于在垂直于膜的膜平面的方向上施加电流的一对电极。 膜包括第一和第二堆叠膜，每个具有钉扎层，中间层和自由层，第二堆叠膜形成在第一堆叠膜上。 膜的轨道宽度方向的侧面成形为在膜的厚度方向上的中间位置具有拐点，并且侧面成形为在基板的上方大致垂直于基板 从拐点。 此外，侧面被成形为在从拐点向基板向下方向接近基板的轨迹宽度上逐渐增加。

公开(公告)号：US20100038700A1

公开(公告)日：2010-02-18

申请号：US12580289

申请日：2009-10-16

申请人： Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu OKAZAKI ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

摘要翻译： 半导体存储器阵列包括具有第一电荷存储层和第一非易失性存储单元的第一非易失性存储单元，第一非易失性存储单元与第一存储单元相邻，具有第二电荷存储层和第二栅电极 。 第一电极和第二电极在垂直于第一方向的第二方向上延伸，第一电极具有在第一方向上朝向第二电极延伸的第一接触部分，并且第二电极具有朝向第一电极的第二接触部分 第一个方向 第一和第二接触位置分别沿第二方向移动，第一电极和第一接触部分与第二电极和第二接触部分电气分离。

公开(公告)号：US07502257B2

公开(公告)日：2009-03-10

申请号：US11797164

申请日：2007-05-01

申请人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

发明人： Tsutomu Okazaki ,  Daisuke Okada ,  Kyoya Nitta ,  Toshihiro Tanaka ,  Akira Kato ,  Toshikazu Matsui ,  Yasushi Ishii ,  Digh Hisamoto ,  Kan Yasui

IPC分类号： G11C11/34

CPC分类号： H01L27/1157 ,  G11C16/0425 ,  H01L21/28282 ,  H01L27/0207 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/0649 ,  H01L29/4234 ,  H01L29/42344 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

摘要： A semiconductor memory array includes a first nonvolatile memory cell having a first charge storage layer and a first gate electrode and a second nonvolatile memory cell, adjacent to the first memory cell in a first direction, having a second charge storage layer and a second gate electrode. The first and second electrodes extend in a second direction perpendicular to the first direction, the first electrode has a first contact section extending toward the second electrode in the first direction, and the second electrode has a second contact section extending toward the first electrode in the first direction. The first and second contact positions are shifted in the second direction, respectively, and the first electrode and the first contact section are electrically separated from the second electrode and the second contact section.

公开(公告)号：US20070040208A1

公开(公告)日：2007-02-22

申请号：US11589095

申请日：2006-10-30

申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

IPC分类号： H01L29/76

CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

公开(公告)号：US07137866B2

公开(公告)日：2006-11-21

申请号：US11267306

申请日：2005-11-07

申请人： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

发明人： Shigeo Moriyama ,  Yoshihiro Ishida ,  Takashi Kugaya ,  Shigeo Ootsuki ,  Soichi Katagiri ,  Sadayuki Nishimura ,  Ryosei Kawai ,  Kan Yasui

IPC分类号： B24B49/00

CPC分类号： B24B53/017 ,  B24B37/042 ,  B24B41/04 ,  B24B53/02 ,  B24B53/12

摘要： The present invention relates to a polishing apparatus, and a semiconductor manufacturing method using the apparatus. Dressing of a grindstone surface is ground by sizing processing whereby dressing of a tool surface can be done while preventing occurrence of cracks on the grindstone surface which is the cause for occurrence of scratches. Further, flatness of the surface of a dressing tool can be guaranteed because of sizing cutting-in; even if a thick grindstone of a few centimeters is used, the flatness can be maintained to the end; and processing with less in-face unevenness can be always carried out. Therefore, the life of the dressing tool can be greatly extended.Further, the present sizing-dressing is carried out jointly with processing of a wafer to thereby enable improvement of throughput of the apparatus as well as maintenance of a processing rate.The present apparatus and method are effective for planarization of various substrate surfaces having irregularities.