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    Fabrication method and structure of semiconductor non-volatile memory device
    1.
    发明授权
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US08084810B2

    公开(公告)日：2011-12-27

    申请号：US12648796

    申请日：2009-12-29

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Fabrication method and structure of semiconductor non-volatile memory device
    2.
    发明授权
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US07671404B2

    公开(公告)日：2010-03-02

    申请号：US11589095

    申请日：2006-10-30

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L29/94

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    FABRICATION METHOD AND STRUCTURE OF SEMICONDUCTOR NON-VOLATILE MEMORY DEVICE 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20100135080A1

    公开(公告)日：2010-06-03

    申请号：US12648796

    申请日：2009-12-29

    申请人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh HISAMOTO ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： G11C16/04 ,  H01L29/792

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Fabrication method and structure of semiconductor non-volatile memory device
    4.
    发明申请
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US20070040208A1

    公开(公告)日：2007-02-22

    申请号：US11589095

    申请日：2006-10-30

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L29/76

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在p型阱中的选择栅极和存储栅极的两侧的区域中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Fabrication method and structure of semiconductor non-volatile memory device
    5.
    发明授权
    Fabrication method and structure of semiconductor non-volatile memory device 有权
    半导体非易失性存储器件的制造方法和结构

    公开(公告)号：US07132718B2

    公开(公告)日：2006-11-07

    申请号：US10726507

    申请日：2003-12-04

    申请人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    发明人： Digh Hisamoto ,  Shinichiro Kimura ,  Kan Yasui ,  Nozomu Matsuzaki

    IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

    CPC分类号： H01L27/11531 ,  H01L21/28282 ,  H01L27/115 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/11568 ,  H01L29/42344 ,  H01L29/792

    摘要： A non-volatile semiconductor memory device with good write/erase characteristics is provided. A selection gate is formed on a p-type well of a semiconductor substrate via a gate insulator, and a memory gate is formed on the p-type well via a laminated film composed of a silicon oxide film, a silicon nitride film, and a silicon oxide film. The memory gate is adjacent to the selection gate via the laminated film. In the regions on the both sides of the selection gate and the memory gate in the p-type well, n-type impurity diffusion layers serving as the source and drain are formed. The region controlled by the selection gate and the region controlled by the memory gate located in the channel region between said impurity diffusion layers have the different charge densities of the impurity from each other.

    摘要翻译： 提供具有良好写入/擦除特性的非易失性半导体存储器件。 通过栅极绝缘体在半导体衬底的p型阱上形成选择栅极，并且通过由氧化硅膜，氮化硅膜和氮化硅膜构成的层叠膜在p型阱上形成存储栅极 氧化硅膜。 存储器栅极通过层叠膜与选择栅极相邻。 在选择栅极的两侧的区域和p型阱的存储栅极中，形成用作源极和漏极的n型杂质扩散层。 由选择栅极控制的区域和由位于所述杂质扩散层之间的沟道区域中的存储栅极控制的区域具有彼此不同的杂质的电荷密度。

    Semiconductor device
    6.
    发明授权
    Semiconductor device 失效
    半导体器件

    公开(公告)号：US08618523B2

    公开(公告)日：2013-12-31

    申请号：US12302740

    申请日：2006-05-31

    申请人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    发明人： Norikatsu Takaura ,  Yuichi Matsui ,  Motoyasu Terao ,  Yoshihisa Fujisaki ,  Nozomu Matsuzaki ,  Kenzo Kurotsuchi ,  Takahiro Morikawa

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  G11C8/08 ,  G11C13/0028 ,  G11C2213/79 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

    摘要： On an insulating film (41) in which a plug (43) as a lower electrode is embedded, a laminated layer pattern of an insulating film (51) made of tantalum oxide, a recording layer (52) made of Ge—Sb—Te based chalcogenide to which indium is introduced and an upper electrode film (53) made of tungsten or tungsten alloy is formed, thereby forming a phase change memory. By interposing the insulating film (51) between the recording layer (52) and the plug (43), an effect of reducing programming current of a phase change memory and an effect of preventing peeling of the recording layer (52) can be achieved. Further, by using the Ge—Sb—Te based chalcogenide to which indium is introduced as the recording layer (52), the difference in work function between the insulating film (51) and the recording layer (52) is increased, and the programming voltage of the phase change memory can be reduced.

    摘要翻译： 在嵌入作为下电极的插头（43）的绝缘膜（41）上，由氧化钽构成的绝缘膜（51）的叠层图案，由Ge-Sb-Te制成的记录层（52） 引入铟的硫属化合物和由钨或钨合金制成的上电极膜（53），从而形成相变存储器。 通过将绝缘膜（51）插入在记录层（52）和插塞（43）之间，可以实现降低相变存储器的编程电流的效果和防止记录层（52）的剥离的效果。 此外，通过使用引入了铟的Ge-Sb-Te类硫族化物作为记录层（52），绝缘膜（51）和记录层（52）之间的功函数差增大，编程 可以减小相变存储器的电压。

    Semiconductor device and method of manufacturing the same
    7.
    发明授权
    Semiconductor device and method of manufacturing the same 有权
    半导体装置及其制造方法

    公开(公告)号：US08546783B2

    公开(公告)日：2013-10-01

    申请号：US13541097

    申请日：2012-07-03

    申请人： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

    发明人： Masahiro Moniwa ,  Nozomu Matsuzaki ,  Riichiro Takemura

    IPC分类号： H01L31/032 ,  H01L45/00

    CPC分类号： H01L45/144 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2213/79 ,  H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/1675

    摘要： A semiconductor device and a method of manufacturing the same with easy formation of a phase change film is realized, realizing high integration and using a phase change film as a memory element. Between a MISFET of a region forming one memory cell and an adjoining MISFET, each MISFET source adjoins in the front surface of an insulating semiconductor substrate. A multi-layer structure of a phase change film and electric conduction film of specific resistance lower than the specific resistance is formed in plan view of the front surface of a semiconductor substrate ranging over each source of both MISFETs, and a plug is stacked thereon. The multi-layer structure functions as a wiring extending and existing in parallel on the surface of the semiconductor substrate, and an electric conduction film sends current in a parallel direction on the surface of the semiconductor substrate.

    摘要翻译： 实现了容易形成相变膜的半导体器件及其制造方法，实现了高集成度和使用相变膜作为存储元件。 在形成一个存储单元的区域的MISFET与相邻的MISFET之间，每个MISFET源在绝缘半导体衬底的前表面相邻。 在两个MISFET的每个源极上的半导体衬底的前表面的平面图中形成具有比电阻率低的电阻率的相变膜和导电膜的多层结构，并且在其上层叠插塞。 多层结构用作在半导体衬底的表面上平行延伸并存在的布线，并且导电膜在半导体衬底的表面上沿平行方向发送电流。