公开(公告)号：US20060145227A1

公开(公告)日：2006-07-06

申请号：US11371743

申请日：2006-03-09

申请人： Josef Willer

发明人： Josef Willer

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119

CPC分类号： H01L27/105 ,  H01L21/28282 ,  H01L27/11568 ,  H01L27/11573

摘要： The invention provides an integration scheme for a memory cell array, especially a charge-trapping memory cell array, comprising an architecture of local interconnects, which enables to avoid nitride insulations of wordline stacks and to produce CMOS devices of different structures and dimensions in standard technology along with the tinier memory cell transistors.

摘要翻译： 本发明提供了一种用于存储单元阵列，特别是电荷捕获存储单元阵列的集成方案，其包括局部互连的架构，其能够避免字线堆叠的氮化物绝缘并且在标准技术中产生不同结构和尺寸的CMOS器件 以及更高级的存储单元晶体管。

公开(公告)号：US07061046B2

公开(公告)日：2006-06-13

申请号：US10952233

申请日：2004-09-28

申请人： Josef Willer ,  Thomas Mikolajick

发明人： Josef Willer ,  Thomas Mikolajick

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/792

摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

摘要翻译： 位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。 至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。 存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。 它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

公开(公告)号：US20060120138A1

公开(公告)日：2006-06-08

申请号：US11260691

申请日：2005-10-28

申请人： Corvin Liaw ,  Josef Willer ,  Michael Kund

发明人： Corvin Liaw ,  Josef Willer ,  Michael Kund

IPC分类号： G11C11/24

CPC分类号： G11C14/00 ,  B82Y10/00 ,  G11C13/0009 ,  G11C13/0014 ,  G11C13/0016 ,  G11C14/0045 ,  H01L27/105 ,  H01L27/10897 ,  H01L27/286 ,  H01L51/0595

摘要： The present invention relates to a semiconductor memory with a volatile memory device, in particular a DRAM memory device, and with a non-volatile memory device. The volatile memory device is electrically coupled with the non-volatile memory device, and the non-volatile memory device has a polymer memory device adapted to be switched between two states of information.

摘要翻译： 本发明涉及具有易失性存储器件，特别是DRAM存储器件以及非易失性存储器件的半导体存储器。 易失性存储器件与非易失性存储器件电耦合，并且非易失性存储器件具有适于在两种信息状态之间切换的聚合物存储器件。

公开(公告)号：US20060091448A1

公开(公告)日：2006-05-04

申请号：US11253939

申请日：2005-10-19

申请人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

发明人： Thomas Mikolajick ,  Hans Reisinger ,  Josef Willer ,  Corvin Liaw

IPC分类号： H01L29/788

CPC分类号： H01L27/11568 ,  G11C16/0466 ,  G11C16/0491 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/7923

摘要： To manufacture a memory device, a gate dielectric layer is formed over a semiconductor body and a gate electrode layer is formed over the gate dielectric layer. The gate electrode layer is structured to form a gate electrode with sidewalls. An etching process is performed to remove parts of the gate dielectric layer from beneath the gate electrode on opposite sides of the gate electrode. Boundary layers, e.g., oxide layers, are formed on an upper surface of the semiconductor body and a lower surface of the gate electrode adjacent where the gate dielectric has been removed thereby leaving spaces. Charge-trapping layer material can then be deposited to fill the spaces. Source and drain regions are then formed in the semiconductor body adjacent the gate electrode.

摘要翻译： 为了制造存储器件，在半导体本体上形成栅极电介质层，并且在栅极介电层上形成栅极电极层。 栅电极层被构造成形成具有侧壁的栅电极。 执行蚀刻处理以从栅极电极的相对侧上的栅电极下方去除栅极电介质层的部分。 边界层，例如氧化物层，形成在半导体本体的上表面上，栅电极的下表面邻近已经去除了栅极电介质，从而留下空间。 然后可以沉积电荷捕获层材料以填充空间。 然后在与栅电极相邻的半导体本体中形成源区和漏区。

公开(公告)号：US20060065921A1

公开(公告)日：2006-03-30

申请号：US10952233

申请日：2004-09-28

申请人： Josef Willer ,  Thomas Mikolajick

发明人： Josef Willer ,  Thomas Mikolajick

IPC分类号： H01L29/76

CPC分类号： H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  H01L27/115 ,  H01L29/792

摘要： Bitline conductor tracks are arranged parallel to one another and electrically insulated from a substrate provided with a basic doping. A memory layer sequence, especially a charge-trapping layer sequence with a dielectric memory layer between dielectric confinement layers, is provided at least in regions adjacent to the bitline conductor tracks. The memory cells comprise gate electrodes connected by wordlines, and channel regions below the gate electrodes. They can be programmed by the trapping of channel hot electrons that are accelerated between source and drain regions formed by induced bitlines that are generated by the application of voltages to the bitline conductor tracks.

摘要翻译： 位线导体轨道彼此平行布置并与具有基本掺杂的衬底电绝缘。 至少在与位线导体轨道相邻的区域中，提供存储层序列，特别是具有在介质约束层之间的介质存储层的电荷俘获层序列。 存储单元包括通过字线连接的栅电极和栅电极下方的沟道区。 它们可以通过捕获通过由通过向位线导体轨道施加电压而产生的感应位线形成的源极和漏极区域之间加速的沟道热电子进行编程。

公开(公告)号：US20050286296A1

公开(公告)日：2005-12-29

申请号：US11145541

申请日：2005-06-03

申请人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

发明人： Michael Bollu ,  Armin Kohlhase ,  Christoph Ludwig ,  Herbert Palm ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  G11C11/34

CPC分类号： H01L27/11568 ,  H01L27/115

摘要： In the case of this semiconductor memory having NROM cells, the channel regions of the memory transistors in each case run transversely with respect to the relevant word line, the bit lines are arranged on the top side of the word lines and in a manner electrically insulated from the latter, and electrically conductive cross-connections are present, which are arranged in sections in interspaces between the word lines and in a manner electrically insulated from the latter and are connected to the bit lines in each case in next but one sequence.

摘要翻译： 在具有NROM单元的半导体存储器的情况下，存储晶体管的沟道区域在每种情况下相对于相关字线横向延伸，位线布置在字线的顶侧并且以电绝缘的方式 并且存在导电交叉连接，这些交叉连接被布置在字线之间的间隔中并且以与后者的电绝缘的方式布置，并且在下一个序列中在每种情况下连接到位线。

公开(公告)号：US20050196923A1

公开(公告)日：2005-09-08

申请号：US11072695

申请日：2005-03-04

申请人： Joachim Deppe ,  Christoph Ludwig ,  Christoph Kleint ,  Josef Willer

发明人： Joachim Deppe ,  Christoph Ludwig ,  Christoph Kleint ,  Josef Willer

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8246 ,  H01L27/115 ,  H01L29/792

CPC分类号： H01L27/11568 ,  H01L21/28282 ,  H01L27/115 ,  H01L29/66833 ,  H01L29/792 ,  H01L29/7926

摘要： A trench (2) is fabricated in a silicon body (1). The walls (4) of the trench are provided with a nitrogen implantation (6). An oxide layer between the source/drain regions (5) and a word line applied on the top side grows to a greater thickness than a lower oxide layer of an ONO storage layer fabricated as gate dielectric at the trench wall. Instead of the nitrogen implantation into the trench walls, it is possible to fabricate a metal silicide layer on the top sides of the source/drain regions in order to accelerate the oxide growth there.

摘要翻译： 在硅体（1）中制造沟槽（2）。 沟槽的壁（4）设置有氮注入（6）。 源极/漏极区域（5）和施加在顶侧的字线之间的氧化物层比在沟槽壁上制作为栅极电介质的ONO存储层的低氧化物层增长更大的厚度。 代替氮注入到沟槽壁中，可以在源极/漏极区的顶侧上制造金属硅化物层，以加速其中的氧化物生长。

公开(公告)号：US06888753B2

公开(公告)日：2005-05-03

申请号：US10680383

申请日：2003-10-06

申请人： Ronald Kakoschke ,  Josef Willer

发明人： Ronald Kakoschke ,  Josef Willer

IPC分类号： G11C16/04 ,  H01L21/8247 ,  H01L21/84 ,  H01L27/115 ,  H01L27/12 ,  G11C11/34

CPC分类号： H01L27/11521 ,  G11C16/0416 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203

摘要： A memory cell array comprises a plurality of memory transistors arranged in a two-dimensional array, each memory transistor having two source/drain regions arranged in a first direction of the memory cell array with a channel substrate region therebetween, and a gate structure arranged above the channel substrate region. The source/drain regions and channel substrate regions are formed in a substrate arranged on an insulating layer, with the channel substrate regions of memory transistors adjacent each other in the first direction being separated from each other by respective source/drain regions extending down to the insulating layer. The source/drain regions and the channel substrate regions of memory transistors adjacent each other in a second direction of the memory cell array furthermore are isolated from each other by trenches filled with insulating material and formed in the substrate so as to extend down to the insulating layer.

摘要翻译： 存储单元阵列包括以二维阵列排列的多个存储晶体管，每个存储晶体管具有沿存储单元阵列的第一方向布置的两个源极/漏极区域，其间具有沟道衬底区域，并且栅极结构布置在 沟道衬底区域。 源极/漏极区域和沟道衬底区域形成在布置在绝缘层上的衬底中，其中在第一方向上彼此相邻的存储晶体管的沟道衬底区域通过相应的源极/漏极区域彼此分开， 绝缘层。 在存储单元阵列的第二方向上彼此相邻的存储晶体管的源极/漏极区域和沟道衬底区域进一步由填充有绝缘材料的沟槽彼此隔离，并形成在衬底中，以向下延伸到绝缘 层。

公开(公告)号：US20050045963A1

公开(公告)日：2005-03-03

申请号：US10894348

申请日：2004-07-19

申请人： Frank Lau ,  Josef Willer

发明人： Frank Lau ,  Josef Willer

IPC分类号： H01L21/8246 ,  H01L27/115 ,  H01L29/423 ,  H01L29/792 ,  G11C11/34

CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L29/792

摘要： A memory cell includes a channel region between source/drain regions at the top side of a semiconductor body and is provided, transversely with respect to the longitudinal direction, with a bulge formed in the semiconductor material. This results in a uniform distribution of the strength of a radially directed electric field and avoids field strength spikes at lateral edges of the channel region. A storage layer sequence is situated between the channel region and the gate electrode as part of a word line.

摘要翻译： 存储单元包括在半导体本体的顶侧的源/漏区之间的沟道区，并且相对于纵向方向横向地设置有形成在半导体材料中的凸起。 这导致径向电场的强度的均匀分布，并且避免了在通道区​​域的横向边缘处的场强尖峰。 存储层序列位于通道区域和栅电极之间，作为字线的一部分。

公开(公告)号：US06800898B2

公开(公告)日：2004-10-05

申请号：US09951239

申请日：2001-09-12

申请人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

发明人： Annalisa Cappelani ,  Bernhard Sell ,  Josef Willer

IPC分类号： H01L2976

CPC分类号： H01L27/10844 ,  H01L27/10861 ,  H01L27/10876

摘要： The bottom and the sides of a lower part of recess formed in the substrate has an insulating structure. A first part of the conductive structure of a first electric conductivity type is located in the lower part of the recess. A second part of the conductive structure of a second electric conductivity type, lower than the first type, is located in an upper part and borders the region of the substrate at the sides of the recess. The conductive structure has a diffusion barrier between its first and second parts. The conductive structure is configured as a bit line of a DRAM cell configuration with a vertical transistor, whereby S/Du represents the lower source/drain area and S/Do represents the upper source/drain area connected to a memory capacitor. Or, the conductive structure is configured as a memory capacitor and the upper source drain/area is connected to a bit line.

摘要翻译： 形成在基板中的凹部的下部的底部和侧面具有绝缘结构。 第一导电类型的导电结构的第一部分位于凹部的下部。 低于第一类型的第二导电类型的导电结构的第二部分位于上部并且在凹部的侧面与基板的区域相邻。 导电结构在其第一和第二部分之间具有扩散阻挡层。 导电结构被配置为具有垂直晶体管的DRAM单元配置的位线，由此S / Du表示下源极/漏极区域，S / Do表示连接到存储电容器的上部源极/漏极区域。 或者，导电结构被配置为存储电容器，并且上部源极漏极/区域连接到位线。