公开(公告)号：US20210226119A1

公开(公告)日：2021-07-22

申请号：US17223025

申请日：2021-04-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on a first sidewall of the MTJ, and a second spacer on a second sidewall of the MTJ. Preferably, the first spacer and the second spacer are asymmetric, the first spacer and the second spacer have different heights, and a top surface of the MTJ includes a reverse V-shape.

公开(公告)号：US11063207B2

公开(公告)日：2021-07-13

申请号：US16589157

申请日：2019-10-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Chen-Yi Weng ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/08 ,  H01L43/12

Abstract: A method for fabricating semiconductor device includes the steps of: forming a substrate having a magnetic tunneling junction (MTJ) region and a logic region; forming a MTJ on the MTJ region; forming a top electrode on the MTJ; forming an inter-metal dielectric (IMD) layer around the MTJ; removing the IMD layer directly on the top electrode to form a recess; forming a first hard mask on the IMD layer and into the recess; removing the first hard mask and the IMD layer on the logic region to form a contact hole; and forming a metal layer in the recess and the contact hole to form a connecting structure on the top electrode and a metal interconnection on the logic region.

公开(公告)号：US11018184B2

公开(公告)日：2021-05-25

申请号：US16532492

申请日：2019-08-06

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Ying-Cheng Liu ,  Yi-Hui Lee ,  Chin-Yang Hsieh ,  Yi-An Shih ,  Jing-Yin Jhang ,  I-Ming Tseng ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01F10/32 ,  H01F41/34 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM), including multiple cell array regions, multiple MRAM cells disposed in the cell array region, a silicon nitride liner conformally covering on the MRAM cells, an atomic layer deposition dielectric layer covering on the silicon nitride liner in the cell array region, wherein the surface of atomic layer deposition dielectric layer is a curved surface concave downward to the silicon nitride liner at the boundary of MRAM cells, and an ultra low-k dielectric layer covering on the atomic layer deposition dielectric layer.

公开(公告)号：US11005030B2

公开(公告)日：2021-05-11

申请号：US16297704

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

公开(公告)号：US20210126191A1

公开(公告)日：2021-04-29

申请号：US16689100

申请日：2019-11-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Hung-Yueh Chen ,  Chen-Yi Weng ,  Si-Han Tsai ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/12 ,  H01L27/22 ,  H01L43/02

Abstract: A method of fabricating a semiconductor device includes the steps of: providing a semiconductor structure including a memory region and a logic region. The semiconductor structure includes a first interlayer dielectric and at least one magnetoresistive random access memory (MRAM) cell disposed on the first interlayer dielectric, and the MRAM cell is disposed in the memory region; depositing a second interlayer dielectric covering the first interlayer dielectric and the at least one MRAM cell; depositing a mask layer conformally covering the second interlayer dielectric; perform a planarization process to remove the mask layer in the memory region; after the step of performing the planarization process, removing the mask layer in the logic region.

公开(公告)号：US20210028351A1

公开(公告)日：2021-01-28

申请号：US17064607

申请日：2020-10-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chia-Chang Hsu ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang

IPC: H01L43/02 ,  H01L43/12 ,  H01L27/22 ,  H01F41/34 ,  H01F10/32 ,  G11C11/16

Abstract: A method for fabricating semiconductor device includes the steps of: forming an inter-metal dielectric (IMD) layer on a substrate; forming a metal interconnection in the IMD layer; forming a bottom electrode layer on the IMD layer, wherein the bottom electrode layer comprises a gradient concentration; forming a free layer on the bottom electrode layer; forming a top electrode layer on the free layer; and patterning the top electrode layer, the free layer, and the bottom electrode layer to form a magnetic tunneling junction (MTJ).

公开(公告)号：US20200266335A1

公开(公告)日：2020-08-20

申请号：US16297704

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  I-Ming Tseng ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: H01L43/02 ,  H01L27/22

Abstract: A semiconductor device preferably includes a metal-oxide semiconductor (MOS) transistor disposed on a substrate, an interlayer dielectric (ILD) layer disposed on the MOS transistor, and a magnetic tunneling junction (MTJ) disposed on the ILD layer. Preferably, a top surface of the MTJ includes a reverse V-shape while the top surface of the MTJ is also electrically connected to a source/drain region of the MOS transistor.

公开(公告)号：US20200227625A1

公开(公告)日：2020-07-16

申请号：US16261524

申请日：2019-01-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Yi-Wei Tseng ,  Meng-Jun Wang ,  Chen-Yi Weng ,  Chin-Yang Hsieh ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Chien-Ting Lin ,  Ying-Cheng Liu ,  Yi-An Shih ,  Yi-Hui Lee ,  I-Ming Tseng

IPC: H01L43/02 ,  H01L27/22

Abstract: A magneto-resistive random access memory (MRAM) cell includes a substrate having a dielectric layer disposed thereon, a conductive via disposed in the dielectric layer, and a cylindrical stack disposed on the conductive via. The cylindrical stack includes a bottom electrode, a magnetic tunneling junction (MTJ) layer on the bottom electrode, and a top electrode on the MTJ layer. A spacer layer is disposed on a sidewall of the cylindrical stack. The top electrode protrudes from a top surface of the spacer layer.

公开(公告)号：US09711368B2

公开(公告)日：2017-07-18

申请号：US13862484

申请日：2013-04-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L21/308 ,  H01L21/66 ,  H01L29/66 ,  H01L21/8238 ,  H01L21/8234 ,  H01L29/78 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/31116 ,  H01L21/823431 ,  H01L21/823821 ,  H01L22/12 ,  H01L22/20 ,  H01L22/26 ,  H01L29/66795 ,  H01L29/785

Abstract: A sidewall image transfer (SIT) process is provided. First, a substrate is provided. A sacrificial layer having a pattern is formed on the substrate. A first measuring step is performed to measure a width of the pattern of the sacrificial layer. A material layer is formed conformally on the sacrificial layer, wherein a thickness of the material layer is adjusted according to the result of the first measuring step. Then, the material layer is removed anisotropically, so the material layer becomes a spacer on a sidewall of the sacrificial layer. Lastly, the sacrificial layer is removed.

公开(公告)号：US09117909B2

公开(公告)日：2015-08-25

申请号：US14470957

申请日：2014-08-28

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Lung-En Kuo ,  Po-Wen Su ,  Chen-Yi Weng ,  Hsuan-Hsu Chen

IPC: H01L29/78 ,  H01L21/762 ,  H01L29/66 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/7851 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/66795 ,  H01L29/7853

Abstract: A method of forming a fin structure is provided. First, a substrate is provided, wherein a first region, a second region encompassing the first region, and a third region encompassing the second region are defined on the substrate. Then, a plurality of first trenches having a first depth are formed in the first region and the second region, wherein each two first trenches defines a first fin structure. The first fin structure in the second region is removed. Lastly, the first trenches are deepened to form a plurality of second trenches having a second depth, wherein each two second trenches define a second fin structure. The present invention further provides a structure of a non-planar transistor.

Abstract translation: 提供一种形成翅片结构的方法。 首先，提供衬底，其中第一区域，包围第一区域的第二区域和包围第二区域的第三区域被限定在衬底上。 然后，在第一区域和第二区域中形成具有第一深度的多个第一沟槽，其中每两个第一沟槽限定第一鳍结构。 第二区域中的第一鳍结构被去除。 最后，加深第一沟槽以形成具有第二深度的多个第二沟槽，其中每两个第二沟槽限定第二鳍结构。 本发明还提供了一种非平面晶体管的结构。