公开(公告)号：US06400625B2

公开(公告)日：2002-06-04

申请号：US09810503

申请日：2001-03-19

申请人： Kazutami Arimoto ,  Hiroki Shimano ,  Katsumi Dosaka

发明人： Kazutami Arimoto ,  Hiroki Shimano ,  Katsumi Dosaka

IPC分类号： G11C700

CPC分类号： G11C29/48

摘要： A test interface circuit carries out an operational test based on a signal input to test pin terminals by directly accessing a DRAM core. A frequency multiplication circuit generates an internal test clock signal by multiplying the frequency of an external test clock signal input to the test pin terminal. A data shifter shifts read data from the DRAM core which operates according to the internal test clock signal in a test mode by N clock cycles (N is an integer of at least 0 determined by column latency) of the internal test clock signal to output the read data from the test pin terminals in synchronization with the external clock test signal.

摘要翻译： 测试接口电路基于通过直接访问DRAM内核来测试引脚端子的信号输入进行操作测试。 倍频电路通过将输入到测试引脚端子的外部测试时钟信号的频率相乘来生成内部测试时钟信号。 数据移位器根据内部测试时钟信号在内部测试时钟信号的N个时钟周期（N为至少为0的整数，由列延迟确定）中，根据测试模式的内部测试时钟信号来移动读取数据，以输出 从外部时钟测试信号同步读取测试引脚端子的数据。

公开(公告)号：US06272034B1

公开(公告)日：2001-08-07

申请号：US09606402

申请日：2000-06-29

申请人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

发明人： Mitsuya Kinoshita ,  Fukashi Morishita ,  Kazutami Arimoto ,  Takeshi Fujino ,  Tetsushi Tanizaki ,  Takahiro Tsuruda ,  Teruhiko Amano ,  Mako Kobayashi

IPC分类号： G11C502

CPC分类号： G11C5/025

摘要： A control circuit portion which controls the operations of memory cells is concentrated in a central portion and heat radiation plates are placed thereon via adhesive. A semiconductor integrated circuit having a function of the MPU or the like is placed above the control circuit portion via a bump electrode. The control circuit portion and a memory block are formed on separate chips respectively.

摘要翻译： 控制存储器单元的操作的控制电路部分集中在中心部分，并且热辐射板通过粘合剂放置在其上。 具有MPU等的功能的半导体集成电路经由凸块电极放置在控制电路部分上方。 控制电路部分和存储块分别形成在分开的芯片上。

公开(公告)号：US06256252B1

公开(公告)日：2001-07-03

申请号：US09659552

申请日：2000-09-11

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： G11C700

CPC分类号： G11C7/22 ,  G11C11/4076 ,  G11C2207/104

摘要： In a sleep mode, data held in a logic circuit is saved to a memory circuit under the control of a transfer control circuit, and thereafter supply of an operation power supply voltage to the logic circuit from a logic power source is stopped. A memory-embedded LSI capable of reducing current consumption in a standby state is provided.

摘要翻译： 在睡眠模式下，保持在逻辑电路中的数据在转移控制电路的控制下被保存到存储器电路，然后停止从逻辑电源向逻辑电路提供操作电源电压。 提供了能够在待机状态下降低电流消耗的存储器嵌入式LSI。

公开(公告)号：US6157052A

公开(公告)日：2000-12-05

申请号：US174315

申请日：1998-10-19

申请人： Shigehiro Kuge ,  Kazutami Arimoto

发明人： Shigehiro Kuge ,  Kazutami Arimoto

IPC分类号： H01L21/822 ,  G11C11/401 ,  H01L21/82 ,  H01L21/8242 ,  H01L23/528 ,  H01L27/04 ,  H01L27/108 ,  H01L27/10

CPC分类号： H01L23/528 ,  H01L27/10805 ,  H01L2924/0002 ,  H01L2924/3011 ,  Y10S257/903

摘要： A high melting point metal wiring layer, a second aluminum wiring layer, and a third aluminum wiring layer are stacked on transistors forming an inverter train of a hierarchical power supply structure respectively. The high melting point metal wiring layer is employed as a local wire for connecting the transistors with each other, the second aluminum wiring layer is employed as a local bus wire and a hierarchical power supply wire, and the third aluminum wiring layer is employed as a main bus wire and a power supply wire to intersect with the respective wires. Consequently, the wiring layers are easy to lay out, while no main bus region is required dissimilarly to the prior art and it is possible to reduce the layout area.

公开(公告)号：US6151244A

公开(公告)日：2000-11-21

申请号：US176029

申请日：1998-10-21

申请人： Takeshi Fujino ,  Kazutami Arimoto

发明人： Takeshi Fujino ,  Kazutami Arimoto

IPC分类号： H01L21/8247 ,  G11C11/401 ,  G11C11/4074 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

CPC分类号： G11C11/401 ,  G11C11/4074

摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

摘要翻译： 由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。 位线接点以规定数量的位线为单位重复移位。 通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。 因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。 因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

公开(公告)号：US5726943A

公开(公告)日：1998-03-10

申请号：US583810

申请日：1996-01-05

申请人： Tadato Yamagata ,  Kazutami Arimoto

发明人： Tadato Yamagata ,  Kazutami Arimoto

IPC分类号： G11C7/06 ,  G11C11/406 ,  G11C11/409 ,  G11C11/4091 ,  G11C7/00 ,  G11C7/02 ,  G11C8/00

CPC分类号： G11C11/4091 ,  G11C11/406 ,  G11C7/065

摘要： A memory cell array of a dynamic semiconductor memory device is divided into a plurality of memory cell blocks. A block selecting circuit selects and refreshes larger number of memory cell blocks in refreshing mode than the number of those selected during normal mode. Sense amplifiers in the memory cell blocks selected by the block selecting circuit are selectively driven with smaller driving force in refreshing mode than that in normal mode. More preferably the driving force is changed during the amplifying operation so as to achieve both the high sensitivity and the suppression of the peak value of the operational current.

摘要翻译： 动态半导体存储器件的存储单元阵列被分成多个存储单元块。 块选择电路在更新模式下选择和刷新大量的在正常模式下选择的存储单元块的数量。 通过块选择电路选择的存储单元块中的感测放大器在刷新模式下以比正常模式更小的驱动力被选择性地驱动。 更优选地，在放大操作期间驱动力被改变，以便实现操作电流的峰值的高灵敏度和抑制。

公开(公告)号：US4982368A

公开(公告)日：1991-01-01

申请号：US463207

申请日：1990-01-10

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： G11C11/401 ,  G11C5/02 ,  G11C7/06 ,  G11C7/18 ,  G11C8/14 ,  G11C11/4097 ,  G11C11/4099 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： G11C7/02 ,  G11C11/4097 ,  G11C11/4099 ,  G11C5/025 ,  G11C7/065 ,  G11C7/18 ,  G11C8/14

摘要： A dynamic semiconductor memory comprising memory cells arranged in a matrix of row and columns, a half of the memory cells being formed into sub-array #1 and the remaining half into sub-array #2. One of a plurality of bit lines included in sub-array #1 and one of a plurality of bit lines included in sub-array #2 constitute a bit line pair. Each of a plurality of word lines corresponding to the columns is divided into a first word line belonging to sub-array #1 and a second word line belonging to sub-array #2. When one of word lines is selected, a potential is applied to one of the first or second word line. As a result, when the information charge of a memory cell is output to certain bit line pair, a reading operation does not take place for the bit lines adjacent thereto, with the latter maintained at a predetermined potential. Thus, the bit line pair is free from the influence of noise due to a potential variation of the adjacent bit lines and the influence of the potential within the bit line pair itself.

摘要翻译： 一种动态半导体存储器，包括以行和列为矩阵排列的存储单元，一半存储单元形成子阵列＃1，剩余的一半形成子阵列＃2。 包括在子阵列＃1中的多个位线之一和子阵列＃2中包括的多个位线之一构成位线对。 对应于列的多个字线中的每一个被划分为属于子数组＃1的第一字线和属于子数组＃2的第二字线。 当选择一行字线时，将电位施加到第一或第二字线之一。 结果，当存储器单元的信息电荷被输出到某个位线对时，与其相邻的位线不会发生读取操作，而后者保持在预定电位。 因此，位线对由于相邻位线的电位变化和位线对内的电位的影响而不受噪声的影响。

公开(公告)号：US4910161A

公开(公告)日：1990-03-20

申请号：US237000

申请日：1988-08-26

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10844 ,  H01L27/10805

摘要： A semiconductor memory comprises a p.sup.- -type semiconductor substrate (1), a p-type epitaxial layer (15) and p.sup.+ -type epitaxial layers (16, 17) formed thereon, an n.sup.+ -type region (6) formed on the p.sup.+ -type epitaxial layer (16) to serve as a bit line, an n.sup.+ -type region (5) formed on the p.sup.+ -type epitaxial layer (17) to serve as a charge storage region and a gate electrode (9) formed on the p-type epitaxial layer (15) to serve as a word line. The p.sup.+ -type epitaxial layers (16, 17) prevent passage of electrons within electron-hole pairs induced by alpha rays, to suppress occurrence of soft errors. The p-type epitaxial layer (15) defines a region corresponding to the channel region of a bus transistor, whereby the impurity concentration thereof can be easily controlled, to readily set the threshold voltage of the bus transistor at an appropriate level.

公开(公告)号：US08188534B2

公开(公告)日：2012-05-29

申请号：US13022864

申请日：2011-02-08

申请人： Fukashi Morishita ,  Kazutami Arimoto

发明人： Fukashi Morishita ,  Kazutami Arimoto

IPC分类号： H01L29/788 ,  H01L27/01 ,  H01L27/12

CPC分类号： G11C11/405 ,  G11C2211/4016 ,  H01L27/108 ,  H01L27/10802

摘要： The present invention aims at providing a semiconductor memory device that can be manufactured by a MOS process and can realize a stable operation. A storage transistor has impurity diffusion regions, a channel formation region, a charge accumulation node, a gate oxide film, and a gate electrode. The gate electrode is connected to a gate line and the impurity diffusion region is connected to a source line. The storage transistor creates a state where holes are accumulated in the charge accumulation node and a state where the holes are not accumulated in the charge accumulation node to thereby store data “1” and data “0”, respectively. An access transistor has impurity diffusion regions, a channel formation region, a gate oxide film, and a gate electrode. The impurity diffusion region is connected to a bit line.

摘要翻译： 本发明的目的在于提供一种可以通过MOS工艺制造并可实现稳定操作的半导体存储器件。 存储晶体管具有杂质扩散区域，沟道形成区域，电荷累积节点，栅极氧化膜和栅电极。 栅电极连接到栅极线，杂质扩散区连接到源极线。 存储晶体管产生在电荷累积节点中积累空穴的状态和空穴未积累在电荷累积节点中的状态，从而分别存储数据“1”和数据“0”。 存取晶体管具有杂质扩散区，沟道形成区，栅极氧化膜和栅电极。 杂质扩散区域连接到位线。

公开(公告)号：US20110006806A1

公开(公告)日：2011-01-13

申请号：US12919356

申请日：2008-12-24

申请人： Kazutami Arimoto

发明人： Kazutami Arimoto

IPC分类号： H03K19/173

CPC分类号： H03K19/17756 ,  H03K19/1733

摘要： An ePLX unit includes a logic unit having an SRAM and a MUX, and a switch unit having an SRAM and a TG for establishing wiring connection in the logic unit. When a composite module is set in the first mode, an Add/Flag control unit uses the SRAMs as a data field and a flag field, respectively, to autonomously control the read address of each of the data field and the flag field in accordance with a control flag stored in the flag field. Furthermore, when the composite module is set in the second mode, the Add/Flag control unit writes configuration information into each of the SRAMs to reconfigure a logic circuit. Consequently, the granularity of the circuit configuration can be rendered variable, which allows improvement in flexibility when configuring a function.

摘要翻译： ePLX单元包括具有SRAM和MUX的逻辑单元，以及具有用于在逻辑单元中建立布线连接的SRAM和TG的开关单元。 当复合模块被设置为第一模式时，加法/标志控制单元分别使用SRAM作为数据字段和标志字段，以依照下述方式自主地控制每个数据字段和标志字段的读取地址 存储在标志字段中的控制标志。 此外，当复合模块被设置为第二模式时，加法/标志控制单元将配置信息写入每个SRAM以重新配置逻辑电路。 因此，电路配置的粒度可以变化，这允许在配置功能时提高灵活性。