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    Semiconductor memory device having row-related circuit operating at high speed
    2.
    发明授权
    Semiconductor memory device having row-related circuit operating at high speed 失效
    具有行相关电路的半导体存储器件以高速工作

    公开(公告)号：US06507532B1

    公开(公告)日：2003-01-14

    申请号：US09722687

    申请日：2000-11-28

    申请人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazunari Inoue ,  Akira Yamazaki ,  Kazutami Arimoto

    IPC分类号： G11C800

    CPC分类号： G11C8/12 ,  G11C8/18 ,  G11C11/4087

    摘要： A central row-related control circuit transmits an internal row address signal to each memory sub block in banks of memory mats asynchronously with an external clock signal, and latches a block selection signal for specifying a memory sub block synchronously with an internal clock signal for one clock cycle period for transmission to each memory sub block. A spare determination circuit performs spare determination asynchronously with the clock signal. A semiconductor memory device easily adaptable to bank expansion without increase of the chip area and capable of implementing a high speed access can be provided.

    摘要翻译： 中央行相关控制电路与外部时钟信号异步地将内部行地址信号发送到存储器存储体中的每个存储器子块，并且与一个内部时钟信号同步地锁存用于指定存储器子块的块选择信号 时钟周期，用于传输到每个存储器子块。 备用确定电路与时钟信号异步地执行备用确定。 可以提供容易适应银行扩张的半导体存储器件，而不增加芯片面积并且能够实现高速存取。

    Dynamic semiconductor memory device
    4.
    发明授权
    Dynamic semiconductor memory device 失效
    动态半导体存储器件

    公开(公告)号：US6151244A

    公开(公告)日：2000-11-21

    申请号：US176029

    申请日：1998-10-21

    申请人： Takeshi Fujino ,  Kazutami Arimoto

    发明人： Takeshi Fujino ,  Kazutami Arimoto

    IPC分类号： H01L21/8247 ,  G11C11/401 ,  G11C11/4074 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  G11C11/24

    CPC分类号： G11C11/401 ,  G11C11/4074

    摘要： Memory cell minimum units (MCU) formed of multi-bit one transistor/one capacitor type memory cells are repeatedly arranged in a column direction, and bit line contacts (BCT) are shifted in the column direction relative to a row direction. The bit line contacts are repeatedly shifted with a prescribed number of bit lines as a unit. A set of a read bit line onto which memory cell data are read and a reference bit line supplying a reference potential can be obtained by controlling the voltage of cell plate lines and bit lines for each set of bit lines. Accordingly, a memory cell occupation area can be reduced and sensing operation in the folded bit line arrangement is possible. Consequently, a memory cell occupation area per one bit can be dramatically reduced and sensing operation in the folded bit line arrangement can be performed.

    摘要翻译： 由多位一晶体管/一电容型存储单元形成的存储单元最小单元（MCU）沿列方向重复排列，并且位线接触（BCT）相对于行方向在列方向上偏移。 位线接点以规定数量的位线为单位重复移位。 通过控制每组位线的单元板线和位线的电压，可以获得读取存储单元数据的读取位线和提供参考电位的参考位线的集合。 因此，可以减小存储器单元占用面积，并且折叠位线布置中的感测操作是可能的。 因此，可以显着减少每一位的存储单元占用面积，并且可以执行折叠位线布置中的感测操作。

    Low-power consumption semiconductor memory device
    7.
    发明申请
    Low-power consumption semiconductor memory device 失效
    低功耗半导体存储器件

    公开(公告)号：US20050041514A1

    公开(公告)日：2005-02-24

    申请号：US10949365

    申请日：2004-09-27

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C11/405 ,  G11C7/12 ,  G11C11/409 ,  G11C11/4094 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  G11C5/00

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    摘要翻译： 存储单元单元包括用于彼此存储互补数据的第一存储元件和第二存储元件。 在选择状态下，第一和第二存储元件分别连接到互补位线。 在待机状态下，位线被预充电到对应于存储在存储单元单元中的数据的电压（Vcc或GND）。 可以实现即使在低电源电压下稳定运行的无刷新，低电流消耗的半导体存储器件。

    Low-power consumption semiconductor memory device
    9.
    发明授权
    Low-power consumption semiconductor memory device 失效

    公开(公告)号：US06636454B2

    公开(公告)日：2003-10-21

    申请号：US09756272

    申请日：2001-01-09

    申请人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    发明人： Takeshi Fujino ,  Kazutami Arimoto ,  Hiroki Shimano

    IPC分类号： G11C700

    CPC分类号： G11C11/4094 ,  G11C7/12

    摘要： A memory cell unit includes a first storage element and a second storage element for storing complementary data with each other. In a selected state, the first and second storage elements are connected to complementary bit lines, respectively at a time. In a standby state, the bit lines are precharged to a voltage (Vccs or GND) corresponding to the data stored in the memory cell unit. Refresh-free, low-current-consumption semiconductor memory device operating stably even under a low power supply voltage can be implemented.

    Semiconductor memory device suitable for merging with logic
    10.
    发明授权
    Semiconductor memory device suitable for merging with logic 失效
    半导体存储器件适用于与逻辑电路合并

    公开(公告)号：US06418067B1

    公开(公告)日：2002-07-09

    申请号：US09592454

    申请日：2000-06-09

    申请人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    发明人： Naoya Watanabe ,  Akira Yamazaki ,  Kazutami Arimoto ,  Takeshi Fujino ,  Isamu Hayashi ,  Hideyuki Noda

    IPC分类号： G11C700

    CPC分类号： G11C29/78 ,  G11C11/4076 ,  G11C29/846

    摘要： Read data line pairs, write data line pairs, a spare read data line pair, and a spare write data line pair are provided extending in the column direction over a memory cell array. Spare bit repair is performed by replacing a data line pair. Column redundancy control circuit changes the timing for outputting the result of spare determination for a data write mode and for a data read mode. A semiconductor memory device suitable for merging with a logic and capable of reducing the current consumption and achieving a higher operation frequency is provided.

    摘要翻译： 读取数据线对，写入数据线对，备用读取数据线对和备用写入数据线对，提供在存储单元阵列上的列方向上延伸。 通过替换数据线对执行备用位修复。 列冗余控制电路改变用于输出数据写入模式和数据读取模式的备用确定结果的定时。 提供一种适于与逻辑并入并能够降低电流消耗并实现更高操作频率的半导体存储器件。