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81.发明授权Element row for slide fastener and method and apparatus for producing the element row and monofilament made of synthetic resin for forming the element row 有权用于拉链的元件排和用于制造由用于形成元件排的合成树脂制成的元件排和单丝的方法和设备
公开(公告)号：US6134756A
公开(公告)日：2000-10-24
申请号：US316333
申请日：1999-05-21
申请人： Yoshio Matsuda
发明人： Yoshio Matsuda
CPC分类号： A44B19/12 , B29C59/043 , B29D5/04 , B29L2031/731 , Y10T24/2518 , Y10T24/2523 , Y10T24/2545
摘要： An element row for a slide fastener made by stamping a monofilament made of synthetic resin. Element coupling heads have a shape which enables the elements to be reliably coupled with each other even though the gaps between upper and lower leg portions of the elements are small. Each coupling head has flat sectional portions extending from center portions of one of the ends of the upper and lower leg portions toward each other, and the flat sectional portions have increasing widths. A coupling portion of the element head is sandwiched between both the flat sectional portions, is thinner than the flat sectional portions, and has tip end portions projecting toward opposite sides in the longitudinal direction of the element row. The coupling portion is reliably engaged in a small gap formed between the coupling heads and the upper and lower leg portions of adjacent elements of a mating element row. An apparatus and method for making the element row is also disclosed.
摘要翻译： 用于通过冲压由合成树脂制成的单丝制成的拉链的元件排。 元件联接头具有能够使元件彼此可靠地连接的形状，即使元件的上腿部和小腿部之间的间隙小。 每个联接头具有从上腿部和下腿部的一个端部的中心部朝向彼此延伸的平坦部分，并且平坦部分具有增加的宽度。 元件头的连接部分夹在两个平坦部分之间，比平坦部分薄，并且具有朝向元件列的纵向方向上的相对侧突出的尖端部分。 联接部可靠地接合在形成在联接头与配合元件列的相邻元件的上下腿部之间的小间隙中。 还公开了一种用于制造元件行的装置和方法。
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82.发明授权Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5867436A
公开(公告)日：1999-02-02
申请号：US803298
申请日：1997-02-20
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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公开(公告)号：US5802883A
公开(公告)日：1998-09-08
申请号：US879817
申请日：1997-06-20
申请人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
发明人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
CPC分类号： A44B19/343 , D04B21/16 , D10B2501/0631 , Y10T24/252
摘要： A knit slide fastener stringer including a fastener tape knitted in a warp-knit ground structure and having along one longitudinal edge an element-attaching portion, and a continuous fastener element row knitted in and along the element-attaching portion of the fastener tape and secured by two or more wales of anchoring chain stitch yarns simultaneously with the knitting of the fastener tape. In this knit slide fastener stringer, successive needle loops of each of the two or more wales formed of the anchoring chain stitch yarns press the continuous fastener element row toward the warp-knit structure of said fastener tape from the upper side, and successive sinker loops constitute part of the ground structure. And a number of warp-inlaid yarns are each laid in and interlaced with at least part of the successive sinker loops. The result is that the ground structure of the element-attaching marginal portion is kept in accurate size to prevent the coupled fastener element rows from locally splitting.
摘要翻译： 一种编织拉链条，其包括以经编织物结构编织的拉链带，并且沿着一个纵向边缘具有元件附接部分，以及沿着拉链带的元件安装部分编织并固定的连续的拉链牙排， 通过拉链带的编织同时固定链式线迹纱线的两个或更多个纵行。 在这种编织拉链条中，由定位链式线迹纱形成的两个或更多个纵行中的每一个的相继的针环从上侧将连续的拉链牙列向着拉链带的经编结构推压，并且连续的沉降弧 构成地面结构的一部分。 并且一些经向嵌入的纱线各自铺设并与至少部分连续的沉降弧相交错。 结果是，元件附接边缘部分的接地结构保持精确的尺寸，以防止联接的紧固件元件排局部分离。
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84.发明授权Random access memory with a plurality amplifier groups for reading and writing in normal and test modes 失效具有多个放大器组的随机存取存储器，用于在正常和测试模式下进行读写
公开(公告)号：US5636163A
公开(公告)日：1997-06-03
申请号：US632967
申请日：1996-04-16
IPC分类号： G11C11/401 , G06F11/267 , G11C7/10 , G11C11/409 , G11C29/00 , G11C29/26 , G11C29/34 , G11C29/38 , G11C7/00
CPC分类号： G11C7/1057 , G11C29/26 , G11C29/38 , G11C7/10 , G11C7/1006 , G11C7/1051 , G11C7/1078 , G11C7/1084 , G06F11/267
摘要： A semiconductor memory device operable for reading and writing in a normal mode and in a test mode is divided into memory cell sections each having blocks of memory cells. Data bus lines are connected to the respective blocks, and switches interconnect data bus lines connected to blocks of the different sections. The switch are made conductive during reading and writing in the normal mode and during writing in the test mode, and nonconductive during reading in the test mode. Input data are applied onto the data bus lines connected one of the blocks for writing in the blocks of the sections simultaneously during writing in the normal mode and in the test mode. In the normal mode, data are read out of the blocks of the sections through the data bus lines connected to the above-mentioned one of the blocks. In the test mode, the data are read out of the blocks of the sections through the data bus lines connected to the respective blocks.
摘要翻译： 可以以正常模式和测试模式读取和写入的半导体存储器件被分成具有存储单元块的存储单元部分。 数据总线连接到相应的块，并且交换连接到不同部分的块的数据总线。 在正常模式下读写时，在测试模式下写入期间开关导通，在测试模式下读取期间不导通。 在正常模式和测试模式下，输入数据被加到连接在一个块上的数据总线上，以便在写入期间同时在这些块中写入。 在正常模式下，通过连接到上述一个块的数据总线，从这些部分的块中读出数据。 在测试模式中，通过连接到相应块的数据总线，从这些部分的块中读出数据。
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公开(公告)号：US5502986A
公开(公告)日：1996-04-02
申请号：US493099
申请日：1995-06-21
申请人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
发明人： Yoshio Matsuda , Hidenobu Kato , Yoshito Ikeguchi
CPC分类号： A44B19/343 , D04B21/16 , D10B2501/0631 , Y10T24/252
摘要： A knit slide fastener including a fastener tape composed of a warp-knit ground structure including chain stitches, and a row of continuous coupling elements knit into and along an element-supporting portion of the fastener tape as the fastener tape is knit, wherein a plurality of threads are knit into the element-supporting portion as binding chain stitches, so as to form a group of successive longitudinally interlocked needle loops appearing on the front side and arranged such that in every two adjacent courses, the preceding needle loop overlies an upper leg of one coupling element, and the succeeding needle loop is disposed in a space between the coupling element and an adjacent coupling element at a position close to the ground structure so as to bend or flex the preceding needle loop into an inverted U shape extending embracingly over the upper and lower legs of the coupling element. With this arrangement, the row of coupling elements can be firmly secured to the ground structure of the fastener tape with high dimensional stability, and can always retain a stable attachment posture to insure the functions required in the slide fastener.
摘要翻译： 一种编织拉链，其包括由针织地面结构构成的拉链带，该拉链带包括链式线迹，以及一排连续的连接元件，当拉链带编织时，该拉链带编织在拉链带的元件支撑部分中并沿着拉链带的元件支撑部分编织; 的螺纹被编织到作为捆绑链式线迹的元件支撑部分中，以形成出现在前侧上的一组连续的纵向互锁的针环，并且布置成使得在每两个相邻的横列中，先前的针环重叠在上腿 的一个耦合元件，并且随后的针环设置在接近于接地结构的位置处的耦合元件和相邻的耦合元件之间的空间中，以便将先前的针环弯曲或弯曲成包围地延伸的倒U形 耦合元件的上腿和下腿。 通过这种布置，可以将这一排联接元件牢固地固定在拉链带的接地结构上，并且可以始终保持稳定的附接姿势，以确保拉链中所需的功能。
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公开(公告)号：US5502985A
公开(公告)日：1996-04-02
申请号：US493094
申请日：1995-06-21
申请人： Yoshio Matsuda , Yoshito Ikeguchi
发明人： Yoshio Matsuda , Yoshito Ikeguchi
CPC分类号： A44B19/343 , D04B21/16 , D10B2501/0631 , Y10T24/252
摘要： A knit slide fastener of the type including a warp-knit fastener tape having a ground structure composed of chain stitches, and a row of continuous coupling elements knit into and along an element-supporting portion of one longitudinal edge portion of the fastener tape as the fastener tape is knit, wherein binding chain stitches are knit into the element-supporting portion to secure the row of coupling elements to the longitudinal tape edge portion, the binding chain stitches having sinker loops urging pairs of legs of the coupling elements toward the element-supporting portion, and needle loops intertwined with needle loops of the chain stitches of the ground structure. With this arrangement, the longitudinal tape edge portion has a knit structure which is relatively tight and substantially non-stretchable in the longitudinal direction. The row of coupling elements attached to such tight and longitudinally non-stretchable longitudinal tape edge portion is highly stable in position and resistant to deformation.
摘要翻译： 这种类型的针织拉链包括具有由链式线迹组成的接地结构的经编拉链带，以及一排连续的联接元件，其编织并沿着拉链带的一个纵向边缘部分的元件支撑部分 拉链带是编织的，其中装订链式针迹编织到元件支撑部分中，以将一排联接元件固定到纵向带边缘部分，该装订链式线迹具有将耦合元件的一对支腿的元件 - 支撑部分和针环与地面结构的链式针迹的针环缠绕。 利用这种布置，纵向带边缘部分具有相对紧密且在纵向方向上基本上不可拉伸的编织结构。 附接到这种紧密和纵向不可拉伸的纵向带边缘部分的连接元件排在位置上是高度稳定的并且抗变形。
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公开(公告)号：US5449591A
公开(公告)日：1995-09-12
申请号：US111110
申请日：1993-08-24
CPC分类号： H05K3/0014 , H05K3/4611 , G03F7/24 , H05K2201/0355 , H05K2201/09018 , H05K2201/09118 , H05K2203/107 , H05K2203/1105 , H05K2203/302 , H05K3/0082 , H05K3/064 , Y10S428/901
摘要： A method for manufacturing a curved surface multi-layer wiring board having highly accurate inner patterns with high reliability. A curved surface multi-layer wiring board is manufactured by providing and pressing a prepreg to form a curved surface, and by plating a copper film on the curved surface. Outer patterns are formed on the copper film. The outer patterns may be formed by a laser exposure process after through-holes are connected between the layers. A method is also provided for repeating the process to obtain a curved surface multi-layer wiring board which has a three dimensional curved surface.
摘要翻译： 一种具有高可靠性的具有高精度内部图案的曲面多层布线板的制造方法。 通过提供并压制预浸料以形成弯曲表面，并通过在弯曲表面上镀覆铜膜来制造曲面多层布线板。 外部图案形成在铜膜上。 外部图案可以在通孔连接在层之间时通过激光曝光工艺形成。 还提供了一种重复该方法以获得具有三维曲面的曲面多层布线板的方法。
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88.发明授权Semiconductor memory device for simple cache system with selective coupling of bit line pairs 失效半导体存储器件，用于具有位线对选择性耦合的简单缓存系统
公开(公告)号：US5353427A
公开(公告)日：1994-10-04
申请号：US63487
申请日：1993-05-19
CPC分类号： G06F12/0893 , G11C7/1021
摘要： A semiconductor memory device comprises a DRAM memory cell array comprising a plurality of dynamic type memory cells arranged in a plurality of rows and columns, and an SRAM memory cell array comprising static type memory cells arranged in a plurality of rows and columns. The DRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns. The SRAM memory cell array is divided into a plurality of blocks each comprising a plurality of columns, corresponding to the plurality of blocks in the DRAM memory cell array. The SRAM memory cell array is used as a cache memory. At the time of cache hit, data is accessed to the SRAM memory cell array. At the time of cache miss, data is accessed to the DRAM memory cell array. On this occasion, data corresponding to one row in each of the blocks in the DRAM memory cell array is transferred to one row in the corresponding block in the SRAM memory cell array.
摘要翻译： 一种半导体存储器件包括：DRAM存储单元阵列，包括以多行和多列布置的多个动态型存储单元;以及SRAM存储单元阵列，其包括排列成多行和列的静态型存储单元。 DRAM存储单元阵列被分成多个块，每个块包括多个列。 SRAM存储单元阵列被分成多个块，每个块包括对应于DRAM存储单元阵列中的多个块的多个列。 SRAM存储单元阵列用作高速缓冲存储器。 在缓存命中时，数据被访问到SRAM存储单元阵列。 在缓存未命中时，数据被存取到DRAM存储单元阵列。 在这种情况下，对应于DRAM存储单元阵列中的每个块中的一行的数据被传送到SRAM存储单元阵列中相应块中的一行。
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公开(公告)号：US5289417A
公开(公告)日：1994-02-22
申请号：US958466
申请日：1992-10-08
IPC分类号： G11C29/00
CPC分类号： G11C29/806 , G11C29/781
摘要： A semiconductor memory device comprises two memory cell arrays (1a, 1b) in which a block divisional operation is performed. Two spare rows (2a, 2b) are provided corresponding to the two memory cell arrays (1a, 1b). Spare row decoders (5a, 5b) are provided for selecting the spare rows (2a, 2b), respectively. One spare row decoder selecting signal generation circuit (18) used in common by the spare row decoders (5a, 5b) is provided. The spare row decoder selecting signal generation circuit (18) can be previously set so as to generate a spare row decoder selecting signal (SRE) when a defective row exists in either of the memory cell arrays (1a, 1b) and the defective row is selected by row decoder groups (4a, 4b). Each of the spare row decoders (5a, 5b) is activated in response to the spare row decoder selecting signal (SRE) and a block control signal.
摘要翻译： 半导体存储器件包括执行块分割操作的两个存储单元阵列（1a，1b）。 对应于两个存储单元阵列（1a，1b）提供两个备用行（2a，2b）。 备用排解码器（5a，5b）分别用于选择备用行（2a，2b）。 提供了由备用行解码器（5a，5b）共同使用的一个备用行解码器选择信号生成电路（18）。 可以预先设置备用行解码器选择信号生成电路（18），以便当在存储单元阵列（1a，1b）中存在有缺陷行时产生备用行译码器选择信号（S（OVS）），并且 有缺陷的行由行解码器组（4a，4b）选择。 每个备用行解码器（5a，5b）响应于备用行解码器选择信号（S（OVS））和块控制信号被激活。
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公开(公告)号：US5185744A
公开(公告)日：1993-02-09
申请号：US479568
申请日：1990-02-14
IPC分类号： G11C29/00 , G11C11/401 , G11C29/28 , G11C29/34 , G11C29/40
摘要： A semiconductor memory device comprises a plurality of memory array blocks (B1 to B4). In each of the plurality of memory array blocks (B1 to B4), a line mode test is performed. Results of the line mode tests performed in the memory array blocks (B1 to B4) are outputted to corresponding match lines (ML1 to ML4). A flag compress (30) performs a logic operation on the test results outputted to the plurality of match lines (ML1 to ML4) and outputs the operation results as test results for the plurality of memory array blocks (B1 to B4) to the outside.
摘要翻译： 半导体存储器件包括多个存储器阵列块（B1至B4）。 在多个存储器阵列块（B1〜B4）的每一个中，进行线路模式测试。 在存储器阵列块（B1〜B4）中执行的线路模式测试的结果被输出到对应的匹配线（ML1〜ML4）。 标志压缩（30）对输出到多个匹配线（ML1〜ML4）的测试结果进行逻辑运算，并将作为多个存储器阵列块（B1〜B4）的测试结果的运算结果输出到外部。
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