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137 条记录 (耗时 0.037 秒)

    Method of manufacturing self-ordered nanochannel-array and method of manufacturing nanodot using the nanochannel-array
    81.
    发明授权
    Method of manufacturing self-ordered nanochannel-array and method of manufacturing nanodot using the nanochannel-array 有权
    使用纳米通道阵列制造自定序纳米通道阵列的方法和制造纳米点的方法

    公开(公告)号：US07282446B2

    公开(公告)日：2007-10-16

    申请号：US10819143

    申请日：2004-04-07

    申请人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

    发明人： In-kyeong Yoo ,  Soo-hwan Jeong ,  Sun-ae Seo ,  In-sook Kim

    IPC分类号： H01L21/302

    CPC分类号： B82B3/00 ,  B29C59/022 ,  B29C59/026 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  H01L21/32139

    摘要： A method of manufacturing a nanochannel-array and a method of fabricating a nanodot using the nanochannel-array are provided. The nanochannel-array manufacturing method includes: performing first anodizing to form a first alumina layer having a channel array formed by a plurality of cavities on an aluminum substrate; etching the first alumina layer to a predetermined depth and forming a plurality of concave portions on the aluminum substrate, wherein each concave portion corresponds to the bottom of each channel of the first alumina layer; and performing second anodizing to form a second alumina layer having an array of a plurality of channels corresponding to the plurality of concave portions on the aluminum substrate. The array manufacturing method makes it possible to obtain finely ordered cavities and form nanoscale dots using the cavities.

    摘要翻译： 提供一种制造纳米通道阵列的方法和使用纳米通道阵列制造纳米点的方法。 纳米通道阵列制造方法包括：执行第一阳极氧化以形成具有由铝基板上的多个空腔形成的沟道阵列的第一氧化铝层; 将第一氧化铝层蚀刻到预定深度并在铝基板上形成多个凹部，其中每个凹部对应于第一氧化铝层的每个通道的底部; 以及进行第二阳极氧化以形成具有与所述铝基板上的所述多个凹部对应的多个通道的阵列的第二氧化铝层。 阵列制造方法使得可以使用空腔获得精细排列的空腔并形成纳米级点。

    Memory device using a transistor and one resistant element for storage
    82.
    发明授权
    Memory device using a transistor and one resistant element for storage 有权
    使用晶体管和一个电阻元件进行存储的存储器件

    公开(公告)号：US06838727B2

    公开(公告)日：2005-01-04

    申请号：US10602736

    申请日：2003-06-25

    申请人： In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

    发明人： In-kyeong Yoo ,  Sun-ae Seo ,  Hyun-jo Kim

    IPC分类号： H01L27/10 ,  G11C11/401 ,  G11C11/404 ,  G11C16/04 ,  H01L21/00 ,  H01L21/822 ,  H01L21/8246 ,  H01L27/112 ,  H01L29/792 ,  H01L31/0328 ,  H01L31/0336 ,  H01L31/072 ,  H01L31/109 ,  H01L49/02

    CPC分类号： H01L27/11206 ,  G11C16/0475 ,  H01L27/112

    摘要： A memory device having one transistor and one resistant element as a storing means and a method for driving the memory device, includes an NPN-type transistor formed on a semiconductor substrate, an interlayer insulating film formed on the semiconductor substrate to cover the transistor in which a contact hole exposing a source region of the transistor is formed, a resistant material in which a bit data “0” or “1” is written connected to the source region of the transistor by a conductive plug or an insulating film, and a conductive plate contacting the resistant material. The memory device exhibits improved degree of integration, reduced current consumption by lengthening a refresh period thereof, and enjoys simplified manufacturing process due to a simple memory cell structure.

    摘要翻译： 具有一个晶体管和一个电阻元件作为存储装置的存储器件和用于驱动存储器件的方法包括形成在半导体衬底上的NPN型晶体管，形成在半导体衬底上以覆盖晶体管的层间绝缘膜， 形成暴露晶体管的源极区域的接触孔，通过导电插塞或绝缘膜将位数据“0”或“1”写入的电阻材料连接到晶体管的源极区域，并且导电 板接触抵抗材料。 存储器件通过延长其刷新周期而呈现出提高的集成度，降低的电流消耗，并且由于简单的存储单元结构而享有简化的制造工艺。

    Graphene electronic devices
    84.
    发明授权
    Graphene electronic devices 有权
    石墨烯电子设备

    公开(公告)号：US09093509B2

    公开(公告)日：2015-07-28

    申请号：US13242177

    申请日：2011-09-23

    申请人： Jin-seong Heo ,  Sun-ae Seo ,  Sung-hoon Lee ,  Hyun-jong Chung ,  Hee-jun Yang

    发明人： Jin-seong Heo ,  Sun-ae Seo ,  Sung-hoon Lee ,  Hyun-jong Chung ,  Hee-jun Yang

    IPC分类号： H01L29/06 ,  H01L29/778 ,  H01L29/16

    CPC分类号： H01L29/778 ,  H01L29/0657 ,  H01L29/1606

    摘要： A graphene electronic device includes a gate electrode, a gate oxide disposed on the gate electrode, a graphene channel layer formed on the gate oxide, and a source electrode and a drain electrode respectively disposed on both ends of the graphene channel layer. In the graphene channel layer, a plurality of nanoholes are arranged in a single line in a width direction of the graphene channel layer.

    摘要翻译： 石墨烯电子器件包括栅电极，设置在栅电极上的栅极氧化物，形成在栅极氧化物上的石墨烯沟道层，以及分别设置在石墨烯沟道层两端的源电极和漏电极。 在石墨烯通道层中，多个纳米孔在石墨烯通道层的宽度方向上以单一线排列。

    Graphene electronic device and method of fabricating the same
    85.
    发明授权
    Graphene electronic device and method of fabricating the same 失效
    石墨烯电子器件及其制造方法

    公开(公告)号：US08421131B2

    公开(公告)日：2013-04-16

    申请号：US12929817

    申请日：2011-02-17

    申请人： Hyun-jong Chung ,  Seung-jae Baek ,  Sun-ae Seo ,  Yun-sung Woo ,  Jin-seong Heo ,  David Seo

    发明人： Hyun-jong Chung ,  Seung-jae Baek ,  Sun-ae Seo ,  Yun-sung Woo ,  Jin-seong Heo ,  David Seo

    IPC分类号： H01L29/78

    CPC分类号： H01L29/66045 ,  H01L23/522 ,  H01L27/0688 ,  H01L27/124 ,  H01L29/1606 ,  H01L29/45 ,  H01L29/7781 ,  H01L29/78684 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A graphene electronic device may include a silicon substrate, connecting lines on the silicon substrate, a first electrode and a second electrode on the silicon substrate, and an interlayer dielectric on the silicon substrate. The interlayer dielectric may be configured to cover the connecting lines and the first and second electrodes and the interlayer dielectric may be further configured to expose at least a portion of the first and second electrodes. The graphene electronic device may further include an insulating layer on the interlayer dielectric and a graphene layer on the insulating layer, the graphene layer having a first end and a second end. The first end of the graphene layer may be connected to the first electrode and the second end of the graphene layer may be connected to the second electrode.

    摘要翻译： 石墨烯电子器件可以包括硅衬底，硅衬底上的连接线，硅衬底上的第一电极和第二电极，以及硅衬底上的层间电介质。 层间电介质可以被配置为覆盖连接线，并且第一和第二电极和层间电介质可以被进一步配置为暴露第一和第二电极的至少一部分。 所述石墨烯电子器件还可以包括在所述层间电介质上的绝缘层和所述绝缘层上的石墨烯层，所述石墨烯层具有第一端和第二端。 石墨烯层的第一端可以连接到第一电极，并且石墨烯层的第二端可以连接到第二电极。

    Memory device and method of manufacturing the same
    88.
    发明授权
    Memory device and method of manufacturing the same 有权
    存储器件及其制造方法

    公开(公告)号：US07491997B2

    公开(公告)日：2009-02-17

    申请号：US11002812

    申请日：2004-12-03

    申请人： In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

    发明人： In-jae Song ,  Won-joo Kim ,  Sun-ae Seo

    IPC分类号： H01L29/76

    CPC分类号： H01L29/792 ,  H01L21/28282 ,  H01L29/66833

    摘要： A memory device and a method of fabricating the same are provided. The method includes forming a gate stack on a semiconductor substrate and partially exposing upper end portions of the semiconductor substrate by etching the gate stack to form a gate stack structure, and implanting a dopant into the exposed portions of the semiconductor substrate to form source and drain regions, wherein the gate stack structure is etched such that its width increases from top to bottom. Accordingly, it is possible to manufacture a memory device with high integration, using a simplified manufacture process.

    摘要翻译： 提供了一种存储器件及其制造方法。 该方法包括在半导体衬底上形成栅极叠层，并通过蚀刻栅叠层来部分地暴露半导体衬底的上端部分以形成栅叠层结构，并将掺杂剂注入半导体衬底的暴露部分以形成源极和漏极 区域，其中蚀刻栅极堆叠结构，使得其宽度从顶部向底部增加。 因此，可以使用简化的制造工艺来制造具有高集成度的存储器件。