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公开(公告)号：US20250118385A1
公开(公告)日：2025-04-10
申请号：US18923244
申请日：2024-10-22
Applicant: Micron Technology, Inc.
Inventor： Chunqiang Weng , Jingwei Cheng
IPC: G11C29/56
Abstract: Methods, systems, and devices for testing circuit for a memory device are described. An apparatus may include a memory system including contacts that route signals to different regions of the memory system. The apparatus may include a first substrate including a memory system interface coupled with the memory system and a probe interface. The apparatus may also include a second substrate coupled with a host system interface of the first substrate and receive the signal of the memory system from the memory system interface. The first interface may route a signal of the memory system to the probe interface and a tester to determine the signal's integrity and any errors associated with the memory system. The first substrate may include a resistor coupled with the contacts of the memory system, the resistor on a surface of the interface may be configured to improve the signal at the tester.
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公开(公告)号：US20250118358A1
公开(公告)日：2025-04-10
申请号：US18746339
申请日：2024-06-18
Applicant: Micron Technology, Inc.
Inventor： Yang Lu , Toby D. Robbs , Christopher J. Kawamura , Kang-Yong Kim
IPC: G11C11/4097 , G11C7/06 , G11C7/18
Abstract: Single (1T) and multi (MT) memory cell architectures may be included in a same memory array. In some embodiments, the individual memory cells of the MT memory cells may have a same polarity. In some embodiments, the individual memory cells of the MT memory cells may have complementary polarity. In some examples, digit lines at memory mats and edge memory mats may be folded for MT memory cells. In some examples, digit lines may be rerouted through local input-output line breaks for the MT memory cells. In some examples, the LIO lines from the MT memory cells may be twisted. In some examples, larger sense amplifiers may be used for the MT memory cells.
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公开(公告)号：US20250118348A1
公开(公告)日：2025-04-10
申请号：US18787824
申请日：2024-07-29
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik
Abstract: An example method can include performing a first sensing operation associated with circuitry on a system on chip (SoC) to determine a first data value, performing a second sensing operation associated with circuitry of a sensor the SoC to determine a second data value, responsive to the first data value and the second data value being the same data value, determining that a clock margin is sufficient, and responsive to the first data value and the second data value being different data values, determining that a clock margin is insufficient. In some examples, a voltage-frequency operating combination associated with at least one operation of the SoC can be adjusted to a particular stored voltage-frequency operating combination that provides a sufficient clocking margin.
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公开(公告)号：US20250118343A1
公开(公告)日：2025-04-10
申请号：US18983986
申请日：2024-12-17
Applicant: Micron Technology, Inc.
Inventor： Dean E. Walker , Tony Brewer
IPC: G06F9/4401
Abstract: A method includes setting an order of input-output channels of a column of a first chiplet of multiple chiplets of a chiplet-based system, wherein one or more of the multiple chiplets include field-configurable input-output channels arranged at a periphery of the chiplets; and programming a second chiplet of the multiple chiplets to change an order of input-output channels of a column of the second chiplet to match the order of input-output channels of the column of the first chiplet.
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公开(公告)号：US20250117659A1
公开(公告)日：2025-04-10
申请号：US18984365
申请日：2024-12-17
Applicant: Micron Technology, Inc.
Inventor： Poorna Kale , Jaime Cummins
Abstract: Systems, devices, and methods related to a deep learning accelerator and memory are described. An integrated circuit may be configured with: a central processing unit, a deep learning accelerator configured to execute instructions with matrix operands; random access memory configured to store first instructions of an artificial neural network executable by the deep learning accelerator and second instructions of an application executable by the central processing unit; one or connections among the random access memory, the deep learning accelerator and the central processing unit; and an input/output interface to an external peripheral bus. While the deep learning accelerator is executing the first instructions to convert sensor data according to the artificial neural network to inference results, the central processing unit may execute the application that uses inference results from the artificial neural network.
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Patent Agency Ranking
公开(公告)号：US20250117289A1
公开(公告)日：2025-04-10
申请号：US18788550
申请日：2024-07-30
Applicant: Micron Technology, Inc.
Inventor： Charles S. Kwong , Seungjune Jeon , Jun Wan
Abstract: Aspects of the present disclosure configure a system component, such as memory sub-system controller, to detect read errors in one or more memory cells using a plurality of read thresholds. The controller selects, for inspection, a target valley of a plurality of valleys associated with an individual memory component of the set of memory components. The controller reads the target valley using a first read threshold to obtain a first set of data and reads the target valley using a second read threshold to obtain a second set of data. The controller compares the first set of data to the second set of data and performs one or more memory operations on the target valley in response to comparing the first set of data to the second set of data.
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公开(公告)号：US20250117209A1
公开(公告)日：2025-04-10
申请号：US18774768
申请日：2024-07-16
Applicant: Micron Technology, Inc.
Inventor： Niccolò Izzo , Alessandro Orlando , Danilo Caraccio
Abstract: Methods, systems, and devices related to firmware validation for firmware updates are disclosed. A controller can, in association with a firmware update of a memory module: determine whether first security information and first customer information of a manifest of a firmware package are valid using second security information and second customer information, respectively, stored by a non-volatile memory device of the memory module; determine whether a first public key of a first image of the firmware package is valid using a second public key of the manifest corresponding to the first image and associated with the first security information and the first customer information; and determine whether a third public key of a second image of the firmware package is valid using a fourth public key of the manifest corresponding to the second image and associated with the first security information and the first customer information.
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公开(公告)号：US20250117143A1
公开(公告)日：2025-04-10
申请号：US18768914
申请日：2024-07-10
Applicant: Micron Technology, Inc.
Inventor： Leon Zlotnik , Leonid Minz
IPC: G06F3/06
Abstract: An intermediate component can be provided between initiator components (from which access requests are originated) and target components (that are to be accessed via the access requests). The intermediate component can encode, decode, and/or bypass the encoding process of address bits to ensure that address bits of the access requests are in a format that is compatible with access of the respective target component.
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公开(公告)号：US20250117137A1
公开(公告)日：2025-04-10
申请号：US18905398
申请日：2024-10-03
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Jay Sarkar , David Scott Ebsen , Aaron Lucas , Seyhan Karakulak , Saeed Sharifi Tehrani
IPC: G06F3/06
Abstract: Systems and methods are disclosed including a memory and a processing device operatively coupled to the memory. The processing device can perform operations including identifying a set of logical addresses associated with data stored on the memory devices in one or more blocks of a first type; determining a temporal metric class associated with the set of logical addresses, wherein the temporal metric class is associated with a corresponding range of predicted update characteristic of the data; identifying, based on the temporal metric class, a set of blocks of a second type, wherein a first block of the first type comprises a first plurality of memory cells having a first number of bits per cell, and wherein a second block of the second type comprises a second plurality of memory cells having a second number of bits per cell that exceeds the first number of bits per cell; and moving the data to the identified set of blocks.
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公开(公告)号：US12272164B2
公开(公告)日：2025-04-08
申请号：US18235149
申请日：2023-08-17
Applicant: Micron Technology, Inc.
IPC: G06F11/00 , G06F1/3225 , G06F11/22 , G06F11/27 , G06V30/16
Abstract: A method for performing automated GUI-driven OpROM validation starts with a processor executing an automated test script; and in response to executing the automated test script, the processor is caused to remotely accessing a memory sub-system using a web driver and an interface. The processor causes a BIOS terminal window of the memory sub-system to be displayed on a display screen. The processor captures a screenshot of the BIOS terminal window and generating an image based on the screenshot. The processor converts the image to text using OCR and generates an output comprising BIOS configuration details based on the text using a machine-learning algorithm. The processor then analyzes the output to validate the memory sub-system when no errors are detected in the output or to flag the memory sub-system when errors are detected in the output. Other embodiments are described herein.
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