-
公开(公告)号：US10971925B2
公开(公告)日：2021-04-06
申请号：US16026503
申请日：2018-07-03
Applicant: STMicroelectronics (Alps) SAS
Inventor： Frederic Lebon , Laurent Chevalier
Abstract: An electronic circuit includes a switch coupled between an input terminal intended to receive a first voltage and an output terminal coupled to a decoupling capacitor and intended to also be coupled to a load. A comparison stage is configured to compare the first voltage and a second voltage that is present at the output terminal. A first adjustment stage is configured to limit a positive inrush current flowing between the input terminal and the output terminal and a second adjustment stage is configured to limit a negative inrush current flowing between the output terminal and the input terminal. A control circuit is configured to activate either the first adjustment stage or the second adjustment stage as a function of a result of the comparison.
-
公开(公告)号：US10917087B2
公开(公告)日：2021-02-09
申请号：US16719053
申请日：2019-12-18
Inventor： Vanni Poletto , David F. Swanson , Giovanni Luca Torrisi , Laurent Chevalier
IPC: H03K17/687 , G01R19/165 , G05B11/42 , G05F1/618 , G05F1/56 , H02J7/34
Abstract: A circuit for controlling a first plurality of transistors connected in parallel and a second plurality of transistors connected in parallel, includes: a first plurality of stages, a respective one of the first plurality of stages being configured to supply a first control signal to a respective one of the first plurality of transistors; and a second plurality of stages, a respective one of the second plurality of stages being configured to supply a second control signal to a respective one of the second plurality of transistors. An output current of the respective one of the first plurality of stages is regulated based on a difference between a first value representative of a sum of output currents of each stage of the first plurality of stages and a second value representative of a sum of set points assigned to the first plurality of stages.
-
公开(公告)号：US20210006215A1
公开(公告)日：2021-01-07
申请号：US16915766
申请日：2020-06-29
Applicant: STMicroelectronics SA , STMicroelectronics (Alps) SAS , STMicroelectronics razvoj polprevodnikov d.o.o.
Inventor： Kosta Kovacic , Christophe Grundrich , Bruno LEDUC , Anton Stern
Abstract: A method for controlling a signal envelope shape of modulation pulses in a driver of a wireless transmitter includes supplying a first voltage to the driver during a non-modulated state, supplying a second voltage configurable by a configurable modulation index value to the driver during a modulated state, switching between the non-modulated state and the modulated state comprising setting the modulation index value to configure the second voltage level at the same level as the first voltage and then switching between supplying the first voltage to the driver and supplying the second voltage to the driver, and filtering to a limited bandwidth the variations of the second voltage resulting from configuring the modulation index value.
-
84.发明授权公开(公告)号：US10832780B2
公开(公告)日：2020-11-10
申请号：US16432369
申请日：2019-06-05
Inventor： Leonardo Valencia Rissetto , Elise Le Roux , Christophe Forel
Abstract: A method can be used for programming a group of memory cells of a non-volatile memory device in a programming window that has a duration longer than a programming duration of a memory cell. The programming window is subdivided into a number of time intervals. A programming profile that was determined by simulation while taking into account a reference criterion is retrieved. The programming profile includes, for each time interval, a maximum number of memory cells that can be triggered for programming within each time interval. The memory device is programmed in the programming window, interval-wise, using the programming profile.
-
公开(公告)号：US10522899B2
公开(公告)日：2019-12-31
申请号：US16017611
申请日：2018-06-25
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01Q1/22 , H01L23/31 , H01L21/56 , H01L23/66 , H01L21/3105 , H01L21/48 , H01L23/498
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
-
Patent Agency Ranking
公开(公告)号：US10520554B2
公开(公告)日：2019-12-31
申请号：US16269331
申请日：2019-02-06
Inventor： Vratislav Michal , Michel Ayraud
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
-
公开(公告)号：US10359800B2
公开(公告)日：2019-07-23
申请号：US15693214
申请日：2017-08-31
Inventor： Serge Ramet , Sandrine Nicolas , Danika Perrin , Cedric Rechatin
Abstract: An integrated circuit includes a first stage configured to receive a bias current. A current regulation loop includes a transimpedance amplifier having a first transistor, and a second transistor having a gate coupled to a gate of the first transistor. The first transistor and the second transistor are configured to compare the bias current with a reference current, and to generate a regulation voltage on an output node of the transimpedance amplifier. A capacitor is coupled between the output node of the transimpedance amplifier and the gates of the first and second transistors.
-
公开(公告)号：US10303192B2
公开(公告)日：2019-05-28
申请号：US15364392
申请日：2016-11-30
Applicant: STMicroelectronics (Alps) SAS
Inventor： Alexandre Pons
IPC: H02J7/00 , G05F1/59 , G05F1/56 , G05F1/569 , H01R24/60 , H02J7/02 , H02J7/06 , H03F3/45 , H01R107/00 , H02J7/10
Abstract: A low dropout voltage regulator unit includes an error amplifier and a power stage having an output terminal that is looped back onto the error amplifier and is capable of delivering an output current to a load. The unit includes multiple main supply inputs that are intended to potentially receive, respectively, multiple different supply voltages. The power stage includes multiple power paths that are connected, respectively, between the main supply inputs and the output terminal, are individually selectable and each comprise an output transistor. The unit also includes a selector circuit connected to the main supply inputs and configured to select one of the power paths according to a selection criterion. The error amplifier includes an output stage configured to selectively control the output transistor of the selected power path.
-
公开(公告)号：US10254781B2
公开(公告)日：2019-04-09
申请号：US15722404
申请日：2017-10-02
Applicant: STMicroelectronics (Alps) SAS
Inventor： Kuno Lenz
Abstract: A voltage source wherein at least one first switch couples a first node of the voltage source to a node of application of at least one potential of a power supply voltage, and at least one first capacitive element couples the first node or a second node of the voltage source to a control node of the first switch.
-
公开(公告)号：US20190067180A1
公开(公告)日：2019-02-28
申请号：US16110121
申请日：2018-08-23
Inventor： David AUCHERE , Laurent SCHWARZ , Deborah COGONI , Eric SAUGIER
IPC: H01L23/498 , H01L23/31 , H01L23/13 , H01L23/00
CPC classification number: H01L23/49838 , H01L21/561 , H01L21/78 , H01L23/13 , H01L23/3128 , H01L23/49822 , H01L23/49833 , H01L23/5389 , H01L24/00 , H01L24/16 , H01L24/97 , H01L2224/16227 , H01L2224/16235 , H05K1/185 , H05K2201/10621 , H05K2201/10636
Abstract: An electronic device includes a support wafer, an electronic chip and an encapsulating block for the electronic chip above the support wafer. The support wafer is provided with a first network of electrical connections and a second network of electrical connections formed solely by tracks. First electrical connection elements are interposed between first front electrical contacts of the electronic chip and rear electrical contacts of the first network. Second electrical connection elements are interposed between second front electrical contacts of the electronic chip and internal electrical contact zones of the tracks of the second network. The first network includes front external electrical contacts and the tracks exhibiting external electrical contact zones.
-
-
-
-
-
-
-
-
-
Search Results
263
records
(took 0.112 seconds)
