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公开(公告)号：US20240266343A1
公开(公告)日：2024-08-08
申请号：US18418051
申请日：2024-01-19
Applicant: STMicroelectronics International N.V.
Inventor： Anuj BHARDWAJ , Anand Kumar MISHRA , Rohit Kumar GUPTA
IPC: H01L27/02 , H01L21/762 , H01L23/538 , H01L29/06
CPC classification number: H01L27/0207 , H01L21/76224 , H01L23/5386 , H01L29/0607
Abstract: An integrated circuit includes a semiconductor substrate patterned to include a first semiconductor track and a second semiconductor track separated from each other by a trench isolation region. The integrated circuit includes a logic circuit including a transistor having a first drain subregion in the first semiconductor track, a second drain subregion in the second semiconductor track, a first source subregion in the first semiconductor track, and a second source subregion in the second semiconductor track. A diffusion bridge of semiconductor material extends between the first and second semiconductor tracks and connects the first source subregion to the second source subregion. The first drain subregion and the second drain subregion are electrically connected by a drain metalization.
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公开(公告)号：US20240265940A1
公开(公告)日：2024-08-08
申请号：US18417588
申请日：2024-01-19
Applicant: STMicroelectronics International N.V.
Inventor： Michele Boscolo Berto , Ezio Galbiati
CPC classification number: G11B5/5569 , G11B19/2009 , H02P7/025
Abstract: Embodiments provide a method of operating a voice coil motor via a transconductance loop. The method includes detecting an actual value of a supply voltage of the transconductance loop. An offset compensation signal of the transconductance loop is produced as a function of the detected actual value of the supply voltage based on a relationship between offset values and the supply voltage of the transconductance loop. The offset compensation signal is applied to a loop control signal of the transconductance loop. A drive current is applied to the voice coil motor. The drive current is related to a target drive current that is based on the loop control signal.
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83.发明公开公开(公告)号：US20240265249A1
公开(公告)日：2024-08-08
申请号：US18105729
申请日：2023-02-03
Applicant: STMicroelectronics International N.V.
Inventor： Danilo Pietro Pau , Prem Kumar Ambrose
IPC: G06N3/08
CPC classification number: G06N3/08
Abstract: Methods, apparatuses, systems, and computer program products for artificial intelligence and machine learning for resource constrained devices and systems, including for classifier learning from a stream of data. A classifier may include a neural network comprised of a plurality of layers with each layer comprised of a plurality of neurons. The neural network may include a hidden layer comprised of a plurality of hidden neurons. In various embodiments, the size of the hidden layer may be constrained and the training of a hidden layer included removing one or more hidden neurons from the hidden layer.
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84.发明授权公开(公告)号：US12046324B2
公开(公告)日：2024-07-23
申请号：US17861458
申请日：2022-07-11
Inventor： Harsh Rawat , Praveen Kumar Verma , Promod Kumar , Christophe Lecocq
CPC classification number: G11C8/10 , G11C7/1087 , G11C7/222 , G11C8/08
Abstract: A memory circuit includes an array of memory cells arranged with first word lines connected to a first sub-array storing less significant bits of data and second word lines connected to a second sub-array storing more significant bits of data. A row decoder circuit coupled to the first and second word lines generates word line signals. A word line gating circuit is configured to selectively gate passage of the word line signals to the second word lines for the second sub-array in response to assertion of a maximum value signal. A data modification circuit performs a mathematical operation on data read from the array of memory cells, and asserts the maximum value signal if the mathematical operation performed on the less significant bits of data from the first sub-array produces a maximum data value.
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85.发明公开公开(公告)号：US20240243945A1
公开(公告)日：2024-07-18
申请号：US18155094
申请日：2023-01-17
Applicant: STMicroelectronics International N.V.
Inventor： Avneep Kumar GOYAL , Nicolas GUION , Sumit Kumar SINGHAL , Jagtar SINGH , Dhulipalla Phaneendra KUMAR
IPC: H04L12/40
CPC classification number: H04L12/40143 , H04L2012/40215
Abstract: Apparatuses and computer-implemented methods for implementing a message-based protocol interface with a communication bus are provided. An example apparatus for implementing a message-based protocol interface with a communication bus may include message handler core circuitry having a transmit message buffer, wherein the transmit message buffer is configured to store a portion of a transmit message. The apparatus may further include receive handler circuitry configured to store a portion of a received message. The apparatus further includes a message handler processor comprising a processor and an instruction memory including program code, the instruction memory and program code configured to, with the processor, cause the message handler processor to transmit at least the portion of the transmit message from a transmit data memory to the message handler core circuitry and receive the received message from the receive handler circuitry into a receive data memory.
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Patent Agency Ranking
公开(公告)号：US20240243698A1
公开(公告)日：2024-07-18
申请号：US18409527
申请日：2024-01-10
Applicant: STMicroelectronics International N.V.
Inventor： Nunzio SPINA , Alessandro CASTORINA , Giuseppe PALMISANO
CPC classification number: H03F1/0233 , H03F3/45475 , H03K5/24 , H03F2200/105
Abstract: An envelope detector receives a modulated signal and a differential stage coupled to the detector produces a replica modulated signal compared to produce a PWM-modulated signal having on and off times. A first switch is actuated to short-circuit the input to the envelope detector. A second switch is actuated to feed back to a storage capacitor a signal indicative of the difference between inputs to the differential stage. A third switch is actuated to short-circuit an input to the comparator. Logic circuitry activates the switched to implement offset compensation where: the first, second and third switches are actuated in the absence of the PWM-modulated signal during start-up and standby phases; and the first, second and third switches are actuated during off times of the PWM-modulated signal in a working phase alternating with the start-up/standby phases.
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公开(公告)号：US12032747B1
公开(公告)日：2024-07-09
申请号：US18167500
申请日：2023-02-10
Applicant: STMicroelectronics International N.V.
Inventor： Stefano Paolo Rivolta , Roberto Mura , Edoardo Nagali
Abstract: The present disclosure is directed to devices and methods for detecting dimming gestures using infrared detection. Infrared signals are detected using a thermal metal-oxide-semiconductor (TMOS) infrared (IR) sensor solution. The TMOS IR sensor is highly accurate and has low power consumptions compared to traditional IR sensors that utilize IR receivers.
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公开(公告)号：US20240213153A1
公开(公告)日：2024-06-27
申请号：US18541497
申请日：2023-12-15
Applicant: STMicroelectronics (Crolles 2) SAS , STMicroelectronics International N.V. , STMicroelectronics France
Inventor： Olivier Weber , Rohit Kumar Gupta , Eric Vandenbossche
IPC: H01L27/092 , H01L23/528 , H01L27/02
CPC classification number: H01L27/0928 , H01L23/528 , H01L27/0207
Abstract: An electronic device including a first active area of a first transistor, a first insulating region forming a first insulation of the first active area, a first insulating gate extending above the first active area and forming a second insulation of the first active area, and a first insulating gate contact coupled to the first insulating gate and positioned above both the first active area and the first insulating region, wherein the first insulating gate contact couples the first insulating gate to a power supply rail.
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公开(公告)号：US12019118B2
公开(公告)日：2024-06-25
申请号：US18186549
申请日：2023-03-20
Inventor： Roberto Colombo , Vivek Mohan Sharma , Samiksha Agarwal
IPC: G01R31/317
CPC classification number: G01R31/31703 , G01R31/31722
Abstract: In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.
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公开(公告)号：US20240204663A1
公开(公告)日：2024-06-20
申请号：US18066765
申请日：2022-12-15
Applicant: STMicroelectronics International N.V.
Inventor： Antonino Torres
Abstract: An integrated circuit device includes: a Buck converter; and a control circuit for the Buck converter, which includes: a comparator configured to compare a feedback voltage of the Buck converter with a reference voltage that increases from a first voltage to a second voltage; a pulse-width modulator configured to generate a pulse-width modulated (PWM) signal having a timing-varying pulse width proportional to the reference voltage; an AND gate configured to generate a first control signal by performing a logic AND operation on an output of the comparator and the PWM signal; a pulse generator configured to generate a second control signal by generating a pulse in response to a rising edge in the output of the comparator; and a selection circuit configured to, based on an output voltage of the Buck converter, select the first control signal or the second control signal as a control signal for the Buck converter.
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