公开(公告)号：US20180048311A1

公开(公告)日：2018-02-15

申请号：US15795912

申请日：2017-10-27

Applicant: Mie Fujitsu Semiconductor Limited

Inventor： Scott E. Thompson ,  Lawrence T. Clark

IPC: H03K19/00 ,  G11C11/412 ,  H01L27/118 ,  H01L29/10

CPC classification number: H03K19/0013 ,  G11C11/412 ,  H01L27/088 ,  H01L27/1104 ,  H01L27/11807 ,  H01L29/1095 ,  H03K19/0948

Abstract: Digital circuits are disclosed that may include multiple transistors having controllable current paths coupled between first and second logic nodes. One or more of the transistors may have a deeply depleted channel formed below its gate that includes a substantially undoped channel region formed over a relatively highly doped screen layer formed over a doped body region. Resulting reductions in threshold voltage variation may improve digital circuit performance. Logic circuit, static random access memory (SRAM) cell, and passgate embodiments are disclosed.

公开(公告)号：US20180040616A1

公开(公告)日：2018-02-08

申请号：US15632815

申请日：2017-06-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Lak Gyo Jeong ,  Yong Rae Cho ,  Kyo Wook Lee ,  Hee Bum Hong

IPC: H01L27/088 ,  H01L27/11

CPC classification number: H01L27/0886 ,  G11C8/16 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104

Abstract: A semiconductor device includes a substrate first through fourth active fins on the substrate, extending in a first direction, and spaced apart from one another in a second direction that intersects the first direction, a first gate electrode extending in the second direction and on the first active fin to overlap with the first active fin but not with the second through fourth active fins, a second gate electrode extending in the second direction and on the second and third active fins to overlap with the second active fin but not with the first and fourth active fins, a first contact on the first gate electrode and connected to a first wordline, and a second contact on the second gate electrode and connected to a second wordline. The first through third active fins are between the first and second contacts. Related devices are also discussed.

公开(公告)号：US09881667B2

公开(公告)日：2018-01-30

申请号：US15375236

申请日：2016-12-12

Applicant: Zeno Semiconductor, Inc.

Inventor： Jin-Woo Han ,  Yuniarto Widjaja

IPC: G11C11/401 ,  G11C15/04 ,  H01L27/108 ,  G11C11/417

CPC classification number: G11C11/417 ,  G11C11/404 ,  G11C11/4091 ,  G11C11/412 ,  G11C15/04 ,  G11C15/043 ,  H01L27/10802

Abstract: A memory cell includes a silicon-on-insulator (SOI) substrate, an electrically floating body transistor fabricated on the silicon-on-insulator (SOI) substrate, and a charge injector region. The floating body transistor is configured to have more than one stable state through an application of a bias on the charge injector region.

公开(公告)号：US20180025774A1

公开(公告)日：2018-01-25

申请号：US15550898

申请日：2015-03-27

Applicant: Institute of Automation Chinese Academy of Sciences

Inventor： Jingqiu Wang ,  Li Liu ,  Liang Chen

IPC: G11C11/417

CPC classification number: G11C11/417 ,  G11C11/412 ,  G11C11/4125 ,  G11C11/413

Abstract: The present invention provides a memory cell of a static random access memory based on resistance reinforcement, which includes a latch circuit and a bit selection circuit. The latch circuit consists of two PMOS transistors P1 and P2, two NMOS transistors N1 and N2, a first resistance-capacitance network and a second resistance-capacitance network. The bit selection circuit consists of NMOS transistors N5 and N6. The latch circuit form four storage nodes X1, X1B, X2, X2B. Compared to the conventional memory cell of a 6T structure, a resistance-capacitance network is added, so that without changing the original read operation circuit and without obviously increasing complexity, the memory cell is prevented from having single event upset at a cost of increasing a small amount of area, thus ensuring correctness of data.

公开(公告)号：US09871056B2

公开(公告)日：2018-01-16

申请号：US15389883

申请日：2016-12-23

Applicant: Tela Innovations, Inc.

Inventor： Scott T. Becker ,  Jim Mali ,  Carole Lambert

IPC: G11C11/412 ,  H01L27/118 ,  H01L27/11 ,  G11C5/06 ,  H01L27/02 ,  H01L27/092 ,  G06F17/50 ,  H01L27/088 ,  H01L23/538 ,  H01L23/498 ,  H01L21/8234 ,  H01L23/528 ,  H01L27/105

CPC classification number: H01L27/11807 ,  G06F17/5068 ,  G06F17/5072 ,  G11C5/06 ,  G11C11/412 ,  H01L21/823475 ,  H01L23/49844 ,  H01L23/528 ,  H01L23/5386 ,  H01L27/0207 ,  H01L27/0218 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1104 ,  H01L2027/11853 ,  H01L2027/11875 ,  H01L2027/11887 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A first conductive structure forms gate electrodes of a first transistor of a first transistor type and a first transistor of a second transistor type. A second conductive structure forms a gate electrode of a second transistor of the first transistor type. A third conductive structure forms a gate electrode of a second transistor of the second transistor type. A fourth conductive structure forms a gate electrode of a third transistor of the first transistor type. A fifth conductive structure forms a gate electrode of a third transistor of the second transistor type. A sixth conductive structure forms gate electrodes of a fourth transistor of the first transistor type and a fourth transistor of the second transistor type. The second and third transistors of the first transistor type and the second and third transistors of the second transistor type are electrically connected to form a cross-coupled transistor configuration.

公开(公告)号：US20180012647A1

公开(公告)日：2018-01-11

申请号：US15711714

申请日：2017-09-21

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hema Ramamurthy ,  Sanjay Parihar ,  Jongsin Yun

IPC: G11C11/412 ,  G11C11/419 ,  H01L27/11 ,  H01L27/12

CPC classification number: G11C11/412 ,  G11C11/419 ,  H01L27/1104 ,  H01L27/1112 ,  H01L27/1203

Abstract: At least one method, apparatus and system disclosed involves a memory device having a memory cell comprising NMOS only transistors. An SRAM bit cell comprises a first pass gate (PG) NMOS transistor coupled to a first bit line signal and a word line signal; a second PG NMOS transistor coupled to a second bit line signal and the word line signal; a first pull down (PD) NMOS transistor operatively coupled to the first PG NMOS transistor; a second PD NMOS transistor operatively coupled to the second PG NMOS transistor; a first pull up (PU) NMOS transistor operatively coupled to the first PD NMOS transistor; and a second PU NMOS transistor operatively coupled to the second PD NMOS transistor. Each of the back gates of the first and second PU NMOS transistors are coupled to a predetermined voltage signal for biasing the first and second PU NMOS transistors.

公开(公告)号：US09865332B2

公开(公告)日：2018-01-09

申请号：US15002207

申请日：2016-01-20

Applicant: Zeno Semiconductor, Inc.

Inventor： Benjamin S. Louie ,  Yuniarto Widjaja ,  Zvi Or-Bach

IPC: G11C11/41 ,  G06F17/50 ,  H01L27/11 ,  G11C8/16 ,  G11C11/419 ,  G11C11/417 ,  G11C11/412

CPC classification number: G11C11/419 ,  G06F17/5045 ,  G06F17/5068 ,  G11C8/16 ,  G11C11/412 ,  G11C11/417 ,  H01L27/11

Abstract: A floating body SRAM cell that is readily scalable for selection by a memory compiler for making memory arrays is provided. A method of selecting a floating body SRAM cell by a memory compiler for use in array design is provided.

公开(公告)号：US09865331B2

公开(公告)日：2018-01-09

申请号：US14710653

申请日：2015-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

Inventor： Mayank Tayal

IPC: G11C11/412 ,  G11C11/419 ,  G11C7/00 ,  G11C7/12 ,  G11C5/06 ,  G11C7/06 ,  G11C11/4091 ,  G11C16/28

CPC classification number: G11C11/419 ,  G11C7/06 ,  G11C7/062 ,  G11C7/065 ,  G11C7/067 ,  G11C7/12 ,  G11C11/4091 ,  G11C11/412

Abstract: A circuit includes a plurality of first circuits, a selection circuit, and a second circuit. The selection circuit is configured to selectively couple a first circuit of the plurality of first circuits with the second circuit. The first circuit includes a first data line and a second data line; and a pair of cross-coupled transistors of a first type coupled with the first data line and the second data line. The second circuit includes a first switching circuit and a second switching circuit; and a pair of cross coupled transistors of a second type different from the first type. The pair of cross-coupled transistors of the first circuit and the pair of cross-coupled transistors of the second circuit are configured as part of a sense amplifier when the first switching circuit and the second switching circuit are turned on.

公开(公告)号：US20170372775A1

公开(公告)日：2017-12-28

申请号：US15587923

申请日：2017-05-05

Applicant: Darryl G. Walker

Inventor： Darryl G. Walker

IPC: G11C11/419

CPC classification number: G11C11/419 ,  G11C5/145 ,  G11C5/147 ,  G11C7/04 ,  G11C7/22 ,  G11C11/412 ,  G11C29/028

Abstract: A method of operating a semiconductor device powered by a first power supply potential can include: generating an assist signal with an enable logic level in response to a voltage window detection circuit indicating the first power supply potential is in a first voltage window at a lower end of an operating range of the semiconductor device and generating the assist signal with a disable logic level in response to the voltage window detection circuit indicating the first power supply potential is in a second voltage window at an upper end of the operating range of the semiconductor device. Read or write operations to an SRAM can have improved reliability when the assist signal has the enable logic level.

公开(公告)号：US09847119B2

公开(公告)日：2017-12-19

申请号：US15266343

申请日：2016-09-15

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Dinesh Chandra ,  Eswararao Potladhurthi ,  Dhani Reddy Sreenivasula Reddy ,  Krishnan S. Rengarajan

IPC: G11C11/419 ,  G11C7/12 ,  G11C11/412

CPC classification number: G11C11/419 ,  G11C7/12 ,  G11C11/412

Abstract: An apparatus and method are provided for implementing write assist with boost attenuation for static random access memory (SRAM) arrays. The apparatus includes a memory array comprising a plurality of SRAM cells. The apparatus further includes a write driver connected to each of a differential pair of bit lines in each of the plurality of SRAM cells of the memory array. The apparatus further includes a write assist attenuation circuit connected to the write driver, the write assist attenuation circuit comprising a clamping device configured to modify a control signal as a function of supply voltage and process to attenuate an amount of boost applied to pull one of the bit lines below ground in an active phase of a write cycle.