公开(公告)号：US09390804B2

公开(公告)日：2016-07-12

申请号：US14522007

申请日：2014-10-23

申请人： Proton World International N.V.

发明人： Ronny Van Keer ,  Youssef Ahssini

IPC分类号： G11C11/34 ,  G11C16/14 ,  G06F12/02 ,  G11C16/34

CPC分类号： G11C16/14 ,  G06F12/0246 ,  G11C16/20 ,  G11C16/26 ,  G11C16/345

摘要： A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

摘要翻译： 更新闪速存储器中的计数器的方法包括第一阶段，其中能够由计数器获取的一组值被编程在闪速存储器的至少一页中。 每当计数器递增/递减时，更新计数器的第二阶段在闪速存储器中编程状态零。

公开(公告)号：US09384842B1

公开(公告)日：2016-07-05

申请号：US14717153

申请日：2015-05-20

申请人： FREESCALE SEMICONDUCTOR, INC.

发明人： Anirban Roy ,  Tom D. Vo

IPC分类号： G11C16/04 ,  G11C16/14 ,  G11C16/34 ,  G11C16/16

CPC分类号： G11C16/14 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3472

摘要： A method of erasing a plurality of non-volatile memory (NVM) cells on a die includes applying erase signals to the plurality of NVM cells. A subset of the plurality of NVM cells is identified to be soft programmed. Information is identified from a non-volatile storage location that stores a value to identify a particular magnitude from a plurality of possible magnitudes of a starting voltage. A soft program signal is applied to the NVM cells identified for soft programming, wherein the starting voltage of the soft program signal has the particular magnitude.

摘要翻译： 擦除芯片上的多个非易失性存储器（NVM）单元的方法包括向多个NVM单元施加擦除信号。 多个NVM单元的子集被识别为软编程。 从非易失性存储位置识别信息，其存储从起始电压的多个可能幅度识别特定幅度的值。 软编程信号被施加到被识别用于软编程的NVM单元，其中软程序信号的起始电压具有特定的大小。

公开(公告)号：US09129700B2

公开(公告)日：2015-09-08

申请号：US13746841

申请日：2013-01-22

申请人： Jon S. Choy

发明人： Jon S. Choy

IPC分类号： G11C7/04 ,  G11C16/34 ,  G11C16/10 ,  G11C16/04 ,  G11C29/02 ,  G11C29/50

CPC分类号： G11C16/345 ,  G11C7/04 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/021 ,  G11C29/028 ,  G11C2029/5002

摘要： Erasing of a non-volatile memory (NVM) having an array of bit cells includes soft programming after an initial erasing of the bit cells. Over-erased bit cells are determined. A temperature is detected. A first soft program gate voltage based on the temperature is provided. Soft programming on the over-erased bit cells using the first soft program gate voltage is performed. Any remaining over-erased bit cells are identified. if there are any remaining over-erased bit cells, soft programming is performed on the remaining over-erased bit cells using a second soft program gate voltage incremented from the first soft program gate voltage.

摘要翻译： 擦除具有位单元阵列的非易失性存储器（NVM）包括在比特单元的初始擦除之后的软编程。 确定过擦除的位单元。 检测到温度。 提供了基于温度的第一软程序栅极电压。 执行使用第一软程序栅极电压对过擦除位单元进行软编程。 识别任何剩余的超擦除位单元。 如果存在任何剩余的过擦除位单元，则使用从第一软程序栅极电压增加的第二软程序栅极电压对剩余的过擦除位单元执行软编程。

公开(公告)号：US20150117106A1

公开(公告)日：2015-04-30

申请号：US14522007

申请日：2014-10-23

申请人： Proton World International N.V.

发明人： Ronny Van Keer ,  Youssef Ahssini

IPC分类号： G11C16/14

CPC分类号： G11C16/14 ,  G06F12/0246 ,  G11C16/20 ,  G11C16/26 ,  G11C16/345

摘要： A method of updating a counter in a flash memory includes a first phase where a set of values capable of being taken by the counter are programmed in at least one page of the flash memory. A second phase of updating the counter programs a state zero in the flash memory each time the counter is incremented/decremented.

摘要翻译： 更新闪速存储器中的计数器的方法包括第一阶段，其中能够由计数器获取的一组值被编程在闪速存储器的至少一页中。 每当计数器递增/递减时，更新计数器的第二阶段在闪速存储器中编程状态零。

公开(公告)号：US08976597B2

公开(公告)日：2015-03-10

申请号：US13227050

申请日：2011-09-07

申请人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

发明人： Yasuhiro Shiino ,  Eietsu Takahashi ,  Koki Ueno

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/16 ,  G11C16/34

CPC分类号： G11C16/16 ,  G11C16/3445 ,  G11C16/345

摘要： A control circuit executes an erase operation that includes an erase pulse application operation and an erase verify operation. The erase pulse application operation applies an erase pulse voltage to a memory cell to change the memory cell from a write state to an erase state. The erase verify operation applies an erase verify voltage to the memory cell to judge whether the memory cell is in the erase state or not. The control circuit changes conditions of execution of the erase verify operation when the number of times of executions of the erase pulse application operation in one erase operation reaches a first number.

摘要翻译： 控制电路执行包括擦除脉冲施加操作和擦除验证操作的擦除操作。 擦除脉冲施加操作将擦除脉冲电压施加到存储单元，以将存储单元从写入状态改变为擦除状态。 擦除验证操作将擦除验证电压施加到存储器单元以判断存储器单元是否处于擦除状态。 当在一个擦除操作中执行擦除脉冲施加操作的次数达到第一数量时，控制电路改变擦除验证操作的执行条件。

公开(公告)号：US20140226407A1

公开(公告)日：2014-08-14

申请号：US14019731

申请日：2013-09-06

申请人： Kabushiki Kaisha Toshiba

发明人： Tatsuo IZUMI

IPC分类号： G11C16/34

CPC分类号： G11C16/344 ,  G11C16/16 ,  G11C16/3445 ,  G11C16/345

摘要： An erase verify operation is executed divided into at least a first erase verify operation and a second erase verify operation. The first erase verify operation is an operation that applies a verify read voltage only to a first group of memory cells among the plurality of memory cells included in the NAND cell unit, and applies a first read pass voltage to memory cells other than the first group of memory cells. The second erase verify operation is an operation that applies the verify read voltage to a second group of memory cells different from the first group of memory cells, and applies a second read pass voltage different from the first read pass voltage to memory cells other than the second group of memory cells.

摘要翻译： 执行擦除验证操作被划分为至少第一擦除验证操作和第二擦除验证操作。 第一擦除验证操作是将验证读取电压仅施加到包括在NAND单元单元中的多个存储单元中的第一组存储单元的操作，并将第一读取通过电压施加到除了第一组之外的存储单元 的记忆细胞。 第二擦除验证操作是将验证读取电压施加到与第一组存储器单元不同的第二组存储器单元的操作，并将不同于第一读取通过电压的第二读取通过电压施加到除 第二组记忆细胞。

公开(公告)号：US20140082437A1

公开(公告)日：2014-03-20

申请号：US13622765

申请日：2012-09-19

申请人： SANDISK TECHNOLOGIES INC.

发明人： Jun Wan ,  Bo Lei ,  Feng Pan ,  Yongke Sun

IPC分类号： G06F12/02 ,  G06F11/00

CPC分类号： G11C16/349 ,  G11C7/1006 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C16/00 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3409 ,  G11C16/3413 ,  G11C16/3418 ,  G11C16/3422 ,  G11C16/3431 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3459 ,  G11C29/025 ,  G11C29/44 ,  G11C2029/1204

摘要： A programming process evaluates NAND strings of a block to detect a defective NAND string, e.g., a NAND string with a defective storage element. Status bits can be stored which identify the defective NAND string. Original data which is to be written in the NAND string is modified so that programming of the defective NAND string does not occur. For example, a bit of write data which requires a storage element in the defective NAND string to be programmed to a higher data state is modified (e.g., flipped) so that no programming of the storage element is required. Subsequently, when a read operation is performed, the flipped bits are flipped back to their original value, such as by using error correction code decoding. In an erase process, a count of defective NAND strings is made and used to adjust a pass condition of a verify test.

摘要翻译： 编程过程评估块的NAND串以检测有缺陷的NAND串，例如具有缺陷存储元件的NAND串。 可以存储识别有缺陷的NAND串的状态位。 要写入NAND串的原始数据被修改，使得不会发生有缺陷的NAND串的编程。 例如，将要编程到较高数据状态的有缺陷的NAND串中的存储元件的一些写入数据修改（例如翻转），使得不需要存储元件的编程。 随后，当执行读取操作时，例如通过使用纠错码解码，将翻转的位翻转回其原始值。 在擦除处理中，进行有缺陷的NAND串的计数并用于调整验证测试的通过条件。

公开(公告)号：US08223558B2

公开(公告)日：2012-07-17

申请号：US13179714

申请日：2011-07-11

申请人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

发明人： Tomoharu Tanaka ,  Hiroshi Nakamura ,  Ken Takeuchi ,  Riichiro Shirota ,  Fumitaka Arai ,  Susumu Fujimura

IPC分类号： G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC分类号： G11C16/0483 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/344 ,  G11C16/3445 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3459 ,  G11C16/3463 ,  G11C2211/5621

摘要： A NAND cell unit includes memory cells which are connected in series. An erase operation is effected on all memory cells. Then, a soft-program voltage, which is opposite in polarity to the erase voltage applied in an erase operation, is applied to all memory cells, thereby setting all memory cells out of an over-erased state. Thereafter, a program voltage of 20V is applied to the control gate of a selected memory cell, 0V is applied to the control gates of the two memory cells provided adjacent to the selected memory cell, and 11V is applied to the control gates of the remaining memory cells. Data is thereby programmed into the selected memory cell. The time for which the program voltage is applied to the selected memory cell is adjusted in accordance with the data to be programmed into the selected memory cell. Hence, data “0” can be correctly programmed into the selected memory cell, multi-value data can be read from any selected memory cell at high speed.

摘要翻译： NAND单元单元包括串联连接的存储单元。 对所有存储单元进行擦除操作。 然后，将与擦除操作中施加的擦除电压极性相反的软编程电压施加到所有存储单元，从而将所有存储单元设置为过擦除状态。 此后，将20V的编程电压施加到所选择的存储单元的控制栅极，将0V施加到与所选存储单元相邻设置的两个存储单元的控制栅极，并且将11V施加到其余的控制栅极 记忆细胞 因此数据被编程到所选择的存储单元中。 根据要编程到所选择的存储单元中的数据来调整对所选存储单元施加编程电压的时间。 因此，可以将数据“0”正确地编程到所选择的存储单元中，可以从任何选择的存储单元高速读取多值数据。

公开(公告)号：US08208337B2

公开(公告)日：2012-06-26

申请号：US12643071

申请日：2009-12-21

申请人： Chun-Yu Liao

发明人： Chun-Yu Liao

IPC分类号： G11C7/00

CPC分类号： G11C16/3409 ,  G11C7/12 ,  G11C7/20 ,  G11C16/345

摘要： An operation method for a memory is provided. The operation method includes: starting a power on procedure on the memory; checking leakage for a bit line of the memory; and if the bit line has leakage, performing a leakage recovery on the bit line until the bit line passes the checking leakage step.

摘要翻译： 提供了一种用于存储器的操作方法。 操作方法包括：在存储器上启动通电程序; 检查存储器的位线的泄漏; 并且如果位线具有泄漏，则在位线上执行泄漏恢复，直到位线通过检查泄漏步骤。

公开(公告)号：US07400537B2

公开(公告)日：2008-07-15

申请号：US11296028

申请日：2005-12-06

申请人： Gerrit Jan Hemink ,  Teruhiko Kamei

发明人： Gerrit Jan Hemink ,  Teruhiko Kamei

IPC分类号： G11C11/34

CPC分类号： G11C11/5628 ,  G11C11/5635 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/16 ,  G11C16/3404 ,  G11C16/3409 ,  G11C16/345 ,  G11C16/3454 ,  G11C16/3468 ,  G11C16/3472 ,  G11C16/3477 ,  G11C2211/5621 ,  G11C2216/18

摘要： A set of non-volatile storage elements is divided into subsets for erasing in order to avoid over-erasing faster erasing storage elements. The entire set of elements is erased until a first subset of the set of elements is verified as erased. The first subset can include the faster erasing cells. Verifying the first subset includes excluding a second subset from verification. After the first subset is verified as erased, they are inhibited from erasing while the second subset is further erased. The set of elements is verified as erased when the second subset is verified as erased. Verifying that the set of elements is erased can include excluding the first subset from verification or verifying both the first and second subsets together. Different step sizes are used, depending on which subset is being erased and verified in order to more efficiently and accurately erase the set of elements.

摘要翻译： 一组非易失性存储元件被划分成用于擦除的子集，以避免擦除存储元件的擦除更快。 整个元素组被擦除，直到该组元素的第一个子集被验证为被擦除为止。 第一个子集可以包括更快的擦除单元。 验证第一个子集包括从验证中排除第二个子集。 在第一子集被验证为擦除之后，它们被禁止擦除，而第二子集被进一步擦除。 当第二个子集被验证为擦除时，该组元素被验证为被擦除。 验证该组元素被擦除可以包括排除第一子集验证或验证第一和第二子集在一起。 使用不同的步长，这取决于要擦除和验证哪个子集，以便更有效和准确地擦除该组元素。