公开(公告)号：US07913645B2

公开(公告)日：2011-03-29

申请号：US11493193

申请日：2006-07-25

申请人： Tatsuya Sato ,  Patricia M. Liu ,  Fanos Christodoulou

发明人： Tatsuya Sato ,  Patricia M. Liu ,  Fanos Christodoulou

IPC分类号： C23C16/00

CPC分类号： H01L21/02 ,  H01J37/32862 ,  H01L21/28202 ,  H01L21/3145 ,  H01L21/31612 ,  H01L21/31641 ,  H01L21/31645 ,  Y10T29/41

摘要： In a first aspect, a first method is provided. The first method includes the steps of (1) preconditioning a process chamber with an aggressive plasma; (2) loading a substrate into the process chamber; and (3) performing plasma nitridation on the substrate within the process chamber. The process chamber is preconditioned using a plasma power that is at least 150% higher than a plasma power used during plasma nitridation of the substrate. Numerous other aspects are provided.

摘要翻译： 在第一方面，提供了第一种方法。 第一种方法包括以下步骤：（1）用积极的等离子体预处理室; （2）将基板装载到处理室中; 和（3）在处理室内的基板上进行等离子体氮化处理。 使用等离子体功率预处理室，该等离子体功率比基板的等离子体氮化期间使用的等离子体功率高至少150％。 提供了许多其他方面。

公开(公告)号：US07910421B2

公开(公告)日：2011-03-22

申请号：US12130646

申请日：2008-05-30

申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

IPC分类号： H01L29/66

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

摘要翻译： 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

公开(公告)号：US07902018B2

公开(公告)日：2011-03-08

申请号：US11861578

申请日：2007-09-26

申请人： Philip Allan Kraus ,  Christopher Olsen ,  Khaled Z. Ahmed

发明人： Philip Allan Kraus ,  Christopher Olsen ,  Khaled Z. Ahmed

IPC分类号： H01L21/8234

CPC分类号： H01L21/3115 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/518

摘要： Embodiments of the present invention generally provide a method for forming a dielectric material with reduced bonding defects on a substrate. In one embodiment, the method comprises forming a dielectric layer having a desired thickness on a surface of a substrate, exposing the substrate to a low energy plasma comprising a fluorine source gas to form a fluorinated dielectric layer on the substrate without etching the dielectric layer, and forming a gate electrode on the substrate. In certain embodiments, the fluorine source gas is a carbon free gas. In certain embodiments, the method further comprises co-flowing a gas selected from the group consisting of argon, helium, N2, O2, and combinations thereof with the fluorine source gas.

摘要翻译： 本发明的实施方案通常提供一种在基片上形成具有降低的结合缺陷的电介质材料的方法。 在一个实施例中，该方法包括在衬底的表面上形成具有所需厚度的电介质层，将衬底暴露于包含氟源气体的低能量等离子体，以在衬底上形成氟化电介质层，而不蚀刻介电层， 以及在所述衬底上形成栅电极。 在某些实施方案中，氟源气体是无碳气体。 在某些实施方案中，该方法还包括将选自氩，氦，N 2，O 2及其组合的气体与氟源气体共流。

公开(公告)号：US07897450B2

公开(公告)日：2011-03-01

申请号：US12355250

申请日：2009-01-16

申请人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

发明人： Fabian Koehler ,  Katy Schabernack ,  Falk Graetsch

IPC分类号： H01L21/8249

CPC分类号： H01L21/31604 ,  H01L21/28176 ,  H01L21/28202 ,  H01L29/518 ,  H01L29/6659 ,  H01L29/7833

摘要： Encapsulation of a gate stack comprising a high-k dielectric material may be accomplished on the basis of a silicon nitride material that is deposited in a sequence of two deposition processes, in which the first process may be performed on the basis of a moderately low process temperature, thereby passivating sensitive surfaces without unduly contaminating the same, while, in a second deposition process, a moderately high process temperature may be used to provide enhanced material characteristics and a reduced overall cycle time compared to conventional ALD or multi-layer deposition techniques.

摘要翻译： 包括高k电介质材料的栅极堆叠的封装可以基于以两个沉积工艺的顺序沉积的氮化硅材料来实现，其中第一工艺可以在适度低的工艺 温度，从而钝化敏感表面，而不会不适当地污染它们，而在第二沉积过程中，与传统的ALD或多层沉积技术相比，可以使用适度高的工艺温度来提供增强的材料特性和减小的总循环时间。

公开(公告)号：US07880242B2

公开(公告)日：2011-02-01

申请号：US11876010

申请日：2007-10-22

申请人： Han Choon Lee

发明人： Han Choon Lee

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/518 ,  H01L21/28088 ,  H01L21/28202 ,  H01L29/4966 ,  H01L29/665 ,  H01L29/6659 ,  H01L29/7833

摘要： A semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a gate insulating layer with a high dielectric constant (k) and a polysilicon layer on a gate metal layer. The gate metal layer can include silicon atoms. Electron mobility can be improved, and production residue and damage can be minimized.

摘要翻译： 提供了一种半导体器件及其制造方法。 半导体器件包括具有高介电常数（k）的栅极绝缘层和栅极金属层上的多晶硅层。 栅极金属层可以包括硅原子。 可以改善电子迁移率，并且可以最小化生产残留和损伤。

公开(公告)号：US07867918B1

公开(公告)日：2011-01-11

申请号：US12046073

申请日：2008-03-11

申请人： Krishnaswamy Ramkumar

发明人： Krishnaswamy Ramkumar

IPC分类号： H01L21/31

CPC分类号： H01L21/28282 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/022 ,  H01L21/02233 ,  H01L21/02271 ,  H01L21/28202 ,  H01L21/28273 ,  H01L21/3143 ,  H01L29/513 ,  H01L29/518

摘要： A semiconductor topography is provided which includes a silicon dioxide layer with a thickness equal to or less than approximately 10 angstroms and a silicon nitride layer arranged upon the silicon dioxide layer. In addition, a method is provided which includes growing an oxide film upon a semiconductor topography in the presence of an ozonated substance and depositing a silicon nitride film upon the oxide film. In some embodiments, the method may include growing the oxide film in a first chamber at a first temperature and transferring the semiconductor topography from the first chamber to a second chamber while the semiconductor topography is exposed to a substantially similar temperature as the first temperature. In either embodiment, the method may be used to form a semiconductor device including an oxide-nitride gate dielectric having an electrical equivalent oxide gate dieletric thickness of less than approximately 20 angstroms.

摘要翻译： 提供半导体形貌，其包括厚度等于或小于约10埃的二氧化硅层和布置在二氧化硅层上的氮化硅层。 此外，提供了一种方法，其包括在存在臭氧化物质的情况下在半导体形貌上生长氧化膜并在氧化物膜上沉积氮化硅膜。 在一些实施例中，该方法可以包括在第一温度下在第一室中生长氧化膜并将半导体形貌从第一室转移到第二室，同时将半导体形貌暴露于与第一温度基本相似的温度。 在任一实施例中，该方法可用于形成半导体器件，其包括具有小于约20埃的电等效氧化物栅极薄膜厚度的氧化物 - 氮化物栅极电介质。

公开(公告)号：US20100323529A1

公开(公告)日：2010-12-23

申请号：US12521645

申请日：2007-12-20

申请人： Minoru Honda ,  Yoshihiro Sato ,  Toshio Nakanishi

发明人： Minoru Honda ,  Yoshihiro Sato ,  Toshio Nakanishi

IPC分类号： H01L21/318 ,  H01L21/314 ,  B05C11/00

CPC分类号： H01L21/28202 ,  H01J37/32192 ,  H01L21/67109 ,  H01L21/67115

摘要： A method for forming an insulating film includes a step of preparing a substrate, which is to be processed and has silicon exposed on the surface; a step of performing first nitriding to the silicon exposed on the surface of the substrate, and forming a silicon nitride film having a thickness of 0.2 nm but not more than 1 nm on the surface of the substrate; and a step of performing first heat treatment to the silicon nitride film in N2O atmosphere and forming a silicon nitride film. This method may further include a step of performing second nitriding to the silicon oxynitride film, and furthermore, may include a step of performing second heat treatment to the silicon oxynitride film after the second nitriding.

摘要翻译： 一种形成绝缘膜的方法包括制备待加工的基片并且在表面上具有硅的步骤; 对在基板表面露出的硅进行第一次氮化，在基板表面形成厚度为0.2nm以上且1nm以下的氮化硅膜的工序; 以及对N 2 O气氛中的氮化硅膜进行第一热处理并形成氮化硅膜的工序。 该方法还可以包括对氮氧化硅膜进行第二氮化的步骤，此外，可以包括在第二次氮化之后对氮氧化硅膜进行第二热处理的步骤。

公开(公告)号：US20100314697A1

公开(公告)日：2010-12-16

申请号：US12861913

申请日：2010-08-24

申请人： James William Adkisson ,  Michael Patrick Chudzik ,  Jeffrey Peter Gambino ,  Hongwen Yan

发明人： James William Adkisson ,  Michael Patrick Chudzik ,  Jeffrey Peter Gambino ,  Hongwen Yan

IPC分类号： H01L29/78

CPC分类号： H01L29/1037 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/42368 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

摘要： A semiconductor structure. The semiconductor structure includes (i) a semiconductor substrate which includes a channel region, (ii) first and second source/drain regions on the semiconductor substrate, (iii) a final gate dielectric region, (iv) a final gate electrode region, and (v) a first gate dielectric corner region. The final gate dielectric region (i) includes a first dielectric material, and (ii) is disposed between and in direct physical contact with the channel region and the final gate electrode region. The first gate dielectric corner region (i) includes a second dielectric material that is different from the first dielectric material, (ii) is disposed between and in direct physical contact with the first source/drain region and the final gate dielectric region, (iii) is not in direct physical contact with the final gate electrode region, and (iv) overlaps the final gate electrode region in a reference direction.

摘要翻译： 半导体结构。 半导体结构包括（i）半导体衬底，其包括沟道区，（ii）半导体衬底上的第一和第二源极/漏极区，（iii）最终栅极电介质区，（iv）最终栅电极区和 （v）第一栅介质角区域。 最后的栅介质区域（i）包括第一电介质材料，和（ii）设置在沟道区域和最终栅电极区域之间并与其直接物理接触。 第一栅介质角区域（i）包括与第一介电材料不同的第二电介质材料，（ii）设置在第一源极/漏极区域和最终栅极电介质区域之间并与之直接物理接触;（iii） ）不与最终栅电极区域直接物理接触，并且（iv）在参考方向上与最终栅电极区域重叠。

公开(公告)号：US20100248464A1

公开(公告)日：2010-09-30

申请号：US12719690

申请日：2010-03-08

申请人： Robert D. Clark

发明人： Robert D. Clark

IPC分类号： H01L21/28

CPC分类号： H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L29/49 ,  H01L29/513

摘要： A method is provided for forming a high-k gate stack with a reduced effective oxide thickness (EOT) for a semiconductor device. The method includes providing a silicon-containing substrate, forming an interface layer on the silicon-containing substrate, where the interface layer has a first equivalent oxide thickness, depositing a first high-k film on the interface layer, and heat-treating the first high-k film and the interface layer at a temperature that forms a modified interface layer, where the modified interface layer has a second equivalent oxide thickness that is equal to or lower than the first equivalent oxide thickness. The method further includes depositing a second high-k film on the modified interface layer. According to one embodiment, the first high-k film includes lanthanum oxide and the second high-k film includes hafnium silicate.

摘要翻译： 提供一种用于形成半导体器件的具有降低的有效氧化物厚度（EOT）的高k栅极堆叠的方法。 该方法包括提供含硅衬底，在含硅衬底上形成界面层，其中界面层具有第一等效氧化物厚度，在界面层上沉积第一高k膜，并将第一 高k膜和界面层，在形成改性界面层的温度下，其中改性界面层具有等于或低于第一等效氧化物厚度的第二等效氧化物厚度。 该方法还包括在修改的界面层上沉积第二高k膜。 根据一个实施方案，第一高k膜包括氧化镧，第二高k膜包括硅酸铪。

公开(公告)号：US20100207203A1

公开(公告)日：2010-08-19

申请号：US12640265

申请日：2009-12-17

申请人： Sang-Yup Han

发明人： Sang-Yup Han

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L21/28202 ,  H01L21/28123 ,  H01L27/10876 ,  H01L29/4236 ,  H01L29/518

摘要： A Semiconductor device includes a substrate having an active region defined by a device isolation layer, a trench formed by etching the active region and the device isolation layer, a buried gate filling a portion of the trench, an interlayer insulation layer formed over the buried gate and filling a remainder of the trench, and an oxidation protecting layer formed between the buried gate and the device isolation layer.

摘要翻译： 半导体器件包括具有由器件隔离层限定的有源区，通过蚀刻有源区和器件隔离层形成的沟槽的衬底，填充沟槽的一部分的掩埋栅，形成在掩埋栅上的层间绝缘层 并填充沟槽的其余部分，以及形成在掩埋栅极和器件隔离层之间的氧化保护层。