公开(公告)号：US07910421B2

公开(公告)日：2011-03-22

申请号：US12130646

申请日：2008-05-30

申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

IPC分类号： H01L29/66

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

摘要翻译： 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

公开(公告)号：US20080305620A1

公开(公告)日：2008-12-11

申请号：US12130646

申请日：2008-05-30

申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeom ,  Gab-jin Nam ,  Sang-bom Kang ,  Sug-hun Hong

IPC分类号： H01L21/425

CPC分类号： H01L21/823857 ,  H01L21/28202 ,  H01L21/31155 ,  H01L29/513 ,  H01L29/518

摘要： Provided is a method of manufacturing a semiconductor device, in which the thickness of a gate insulating layer of a CMOS device can be controlled. The method can include selectively injecting fluorine (F) into a first region on a substrate and avoiding injecting the fluorine (F) into a second region on the substrate. A first gate insulating layer is formed of oxynitride layers on the first and second regions to have first and second thicknesses, respectively, where the first thickness is less than the second thickness. A second gate insulating layer is formed on the first gate insulating layer and a gate electrode pattern is formed on the second gate insulating layer.

摘要翻译： 提供一种制造半导体器件的方法，其中可以控制CMOS器件的栅极绝缘层的厚度。 该方法可以包括将氟（F）选择性地注入到衬底上的第一区域中，并且避免将氟（F）注入到衬底上的第二区域中。 第一栅极绝缘层由第一和第二区域上的氧氮化物层形成，以分别具有第一和第二厚度，其中第一厚度小于第二厚度。 在第一栅极绝缘层上形成第二栅极绝缘层，并且在第二栅极绝缘层上形成栅电极图案。

公开(公告)号：US20080116530A1

公开(公告)日：2008-05-22

申请号：US11855413

申请日：2007-09-14

申请人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

发明人： Sang-jin Hyun ,  Si-young Choi ,  In-sang Jeon ,  Sang-bom Kang ,  Hye-min Kim

IPC分类号： H01L29/94 ,  H01L21/8238

CPC分类号： H01L21/823828 ,  H01L21/823437 ,  H01L21/82345 ,  H01L21/823462 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10894 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66621

摘要： A semiconductor device may include a semiconductor substrate and first and second transistors. The first transistor may have a first gate structure on the semiconductor substrate, and the first gate structure may include a first gate insulating layer between a first gate electrode and the semiconductor substrate. The first gate insulating layer may include first and second dielectric materials with the second dielectric material having a greater dielectric constant than the first dielectric material. Moreover, the first gate electrode may be in contact with the second dielectric material. The second transistor may have a second gate structure on the semiconductor substrate, with the second gate structure including a second gate insulating layer between a second gate electrode and the semiconductor substrate. Related methods are also discussed.

摘要翻译： 半导体器件可以包括半导体衬底和第一和第二晶体管。 第一晶体管可以在半导体衬底上具有第一栅极结构，并且第一栅极结构可以包括在第一栅极电极和半导体衬底之间的第一栅极绝缘层。 第一栅极绝缘层可以包括第一和第二介电材料，其中第二介电材料具有比第一介电材料更大的介电常数。 此外，第一栅电极可以与第二电介质材料接触。 第二晶体管可以在半导体衬底上具有第二栅极结构，其中第二栅极结构包括在第二栅电极和半导体衬底之间的第二栅极绝缘层。 还讨论了相关方法。

公开(公告)号：US08367502B2

公开(公告)日：2013-02-05

申请号：US12654337

申请日：2009-12-17

申请人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

发明人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

IPC分类号： H01L21/8234

CPC分类号： H01L21/823842 ,  H01L21/82385

摘要： The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.

摘要翻译： 该方法包括提供包括将要形成不同的导电金属氧化物半导体（MOS）晶体管的第一和第二区域的半导体衬底。 在所述半导体衬底上方的栅极电介质层，其顺序地在所述栅极电介质层上方形成第一金属导电层和第二金属导电层; 用掩模覆盖第二区域，并且将第一材料离子种植到第一区域的第一金属导电层中。 通过图案化第一区域的栅介电层和第一金属导电层，去除第一区域的第二金属导电层并形成第一区域的第一栅极电极和第二区域的第二栅极电极，以及栅极电介质 第一金属导电层和第二区域的第二金属导电层。 由于第一和第二区域的栅电极具有不同的厚度，并且第一和第二栅电极中的至少一个包括杂质，所以具有不同功函数的半导体衬底的第一和第二区域。

公开(公告)号：US20110121399A1

公开(公告)日：2011-05-26

申请号：US12873611

申请日：2010-09-01

申请人： Hong-bae PARK ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-ju Na ,  Hye-lan Lee ,  Hyung-seok Hong

发明人： Hong-bae PARK ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-ju Na ,  Hye-lan Lee ,  Hyung-seok Hong

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L27/092 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/7833

摘要： A complementary metal oxide semiconductor (CMOS) device including: a semiconductor substrate including a NMOS region and a PMOS region; a NMOS metal gate stack structure on the NMOS region and including a first high dielectric layer, a first barrier metal gate on the first high dielectric layer and including a metal oxide nitride layer, and a first metal gate on the first barrier metal gate; and a PMOS metal gate stack structure on the PMOS region and including a second high dielectric layer, a second barrier metal gate on the second high dielectric layer and including a metal oxide nitride layer, and a second metal gate on the second barrier metal gate.

摘要翻译： 一种互补金属氧化物半导体（CMOS）器件，包括：包括NMOS区域和PMOS区域的半导体衬底; 在NMOS区域上的NMOS金属栅叠层结构，包括第一高介电层，第一高电介质层上的第一势垒金属栅极，并且包括金属氧化物氮化物层，以及第一栅极金属栅极上的第一金属栅极; 以及在PMOS区域上的PMOS金属栅极堆叠结构，并且包括第二高介电层，第二高介电层上的第二阻挡金属栅极，并且包括金属氧化物氮化物层，以及在第二阻挡金属栅极上的第二金属栅极。

公开(公告)号：US08932922B2

公开(公告)日：2015-01-13

申请号：US13116045

申请日：2011-05-26

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/8238 ,  H01L29/51 ,  H01L21/28

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US08293599B2

公开(公告)日：2012-10-23

申请号：US12540090

申请日：2009-08-12

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/8238

CPC分类号： H01L21/823857 ,  H01L21/823842

摘要： A semiconductor device that has a dual gate having different work functions is simply formed by using a selective nitridation. A gate insulating layer is formed on a semiconductor substrate including a first region and a second region, on which devices having different threshold voltages are to be formed. A diffusion inhibiting material is selectively injected into the gate insulating layer in one of the first region and the second region. A diffusion layer is formed on the gate insulating layer. A work function controlling material is directly diffused from the diffusion layer to the gate insulating layer using a heat treatment, wherein the gate insulting layer is self-aligned capped with the selectively injected diffusion inhibiting material so that the work function controlling material is diffused into the other of the first region and the second region. The gate insulating layer is entirely exposed by removing the diffusion layer. A gate electrode layer is formed on the exposed gate insulating layer. A first gate and a second gate having different work functions are respectively formed in the first region and the second region by etching the gate electrode layer and the gate insulating layer.

摘要翻译： 具有不同工作功能的双栅极的半导体器件通过使用选择性氮化简单地形成。 在包括第一区域和第二区域的半导体衬底上形成栅极绝缘层，在其上形成具有不同阈值电压的器件。 扩散抑制材料被选择性地注入到第一区域和第二区域之一中的栅极绝缘层中。 在栅极绝缘层上形成扩散层。 工作功能控制材料通过热处理从扩散层直接扩散到栅极绝缘层，其中栅极绝缘层由选择性注入的扩散抑制材料自对准封盖，使得功函数控制材料扩散到 第一个地区和第二个地区的其他地区。 通过去除扩散层，完全暴露栅极绝缘层。 在暴露的栅极绝缘层上形成栅极电极层。 通过蚀刻栅极电极层和栅极绝缘层，分别在第一区域和第二区域中形成具有不同功函数的第一栅极和第二栅极。

公开(公告)号：US20100203716A1

公开(公告)日：2010-08-12

申请号：US12580302

申请日：2009-10-16

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/28 ,  H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。

公开(公告)号：US20100164009A1

公开(公告)日：2010-07-01

申请号：US12654337

申请日：2009-12-17

申请人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

发明人： Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hoon-joo Nah ,  Hyung-seok Hong

IPC分类号： H01L27/092 ,  H01L21/8238 ,  H01L27/088

CPC分类号： H01L21/823842 ,  H01L21/82385

摘要： The method involves providing a semiconductor substrate comprising first and second regions in which different conductive metal-oxide semiconductor (MOS) transistors are to be formed. A gate dielectric layer above the semiconductor substrate sequentially forming a first metallic conductive layer and a second metallic conductive layer on and above the gate dielectric layer; covering the second region with a mask, and performing ion plantation of a first material into the first metallic conductive layer of the first region. Removing the second metallic conductive layer of the first region and forming a first gate electrode of the first region and a second gate electrode of the second region by patterning the gate dielectric layer and the first metallic conductive layer of the first region, and the gate dielectric layer, the first metallic conductive layer, and the second metallic conductive layer of the second region. The first and second regions of the semiconductor substrate having different work functions because the gate electrodes of the first and second regions have different thicknesses and at least one of the first and second gate electrodes include impurities.

摘要翻译： 该方法包括提供包括将要形成不同的导电金属氧化物半导体（MOS）晶体管的第一和第二区域的半导体衬底。 在所述半导体衬底上方的栅极电介质层，其顺序地在所述栅极电介质层上方形成第一金属导电层和第二金属导电层; 用掩模覆盖第二区域，并且将第一材料离子种植到第一区域的第一金属导电层中。 通过图案化第一区域的栅介电层和第一金属导电层，去除第一区域的第二金属导电层并形成第一区域的第一栅极电极和第二区域的第二栅极电极，以及栅极电介质 第一金属导电层和第二区域的第二金属导电层。 由于第一和第二区域的栅电极具有不同的厚度，并且第一和第二栅电极中的至少一个包括杂质，所以具有不同功函数的半导体衬底的第一和第二区域。

公开(公告)号：US20110223758A1

公开(公告)日：2011-09-15

申请号：US13116045

申请日：2011-05-26

申请人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

发明人： Hoon-joo Na ,  Yu-gyun Shin ,  Hong-bae Park ,  Hag-ju Cho ,  Sug-hun Hong ,  Sang-jin Hyun ,  Hyung-seok Hong

IPC分类号： H01L21/336

CPC分类号： H01L21/823828 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/32133 ,  H01L21/324 ,  H01L21/823437 ,  H01L21/823842 ,  H01L21/823857 ,  H01L27/0922 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518

摘要： A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

摘要翻译： 制造具有双栅极的半导体器件的方法允许栅极具有各种阈值电压。 该方法包括：跨越衬底上的第一区域和第二区域以上述顺序形成栅极绝缘层，第一覆盖层和阻挡层，通过去除第一覆盖层和暴露第一区域上的栅极绝缘层; 所述阻挡层从所述第一区域形成在所述第一区域中的所述栅极绝缘层上和所述第二区域中的所述势垒层上形成第二覆盖层，并对形成有所述第二覆盖层的所述基板进行热处理。 热处理使得第二覆盖层的材料扩散到第一区域中的栅极绝缘层中，并且第一覆盖层的材料扩散到第二区域中的栅极绝缘层中。 因此，可以在第一和第二区域中形成具有不同阈值电压的器件。