公开(公告)号：US07755441B1

公开(公告)日：2010-07-13

申请号：US12203871

申请日：2008-09-03

Applicant: Kenneth R. Cioffi ,  Didier Lacroix

Inventor： Kenneth R. Cioffi ,  Didier Lacroix

IPC: H03B5/30

CPC classification number: H03C3/0925 ,  H03B5/04 ,  H03C3/0933 ,  H03C3/0991 ,  H03L1/022 ,  H03L1/026 ,  H03L7/1976

Abstract: A signal generation technique is based on a reference frequency provided by a MEMS resonator. The signal generation technique compensates for temperature- and fabrication process-induced frequency variations collectively. In some embodiments, a device implementing the disclosed signal generation technique includes a fractional-N synthesizer, a temperature sensor, calibration data, and a sigma-delta modulator to adjust the reference frequency of the MEMS resonator to a desired frequency value while compensating for the temperature variation of the MEMS resonator.

Abstract translation: 信号产生技术基于由MEMS谐振器提供的参考频率。 信号发生技术统一地补偿温度和制造过程引起的频率变化。 在一些实施例中，实现公开的信号生成技术的装置包括分数N合成器，温度传感器，校准数据和Σ-Δ调制器，以将MEMS谐振器的参考频率调整到期望的频率值，同时补偿 MEMS谐振器的温度变化。

公开(公告)号：US07750750B2

公开(公告)日：2010-07-06

申请号：US12115068

申请日：2008-05-05

Applicant: Sofoklis Plevridis ,  Theodoros Georgantas ,  Konstantinos D. Vavelidis

Inventor： Sofoklis Plevridis ,  Theodoros Georgantas ,  Konstantinos D. Vavelidis

IPC: H03C3/00

CPC classification number: H03C5/00 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958

Abstract: Enhanced polar modulator for transmitter. Within a phase locked loop (PLL), a two point modulation topology is employed in which phase information passes through a limiter (e.g., a +90° or +re/2) in which the phase information dynamic range is divide by a factor (e.g., by 2) and a maximum frequency deviation is also divided by a factor (e.g., by 2). Then, a double balanced up-converter mixer/modulator is implemented to perform gain adjustment (e.g., magnitude and/or amplitude adjustment) and phase changes of 0° and +180° or 0 and +re (e.g., negative gains values may be employed). Phase adjustment in such an architecture is split and provided to both the PLL and to the mixer/modulator of such a polar modulator within a transmitter module such as may be implemented within a communication device (e.g., which may be a wireless communication device). This architecture that includes a PLL with a double balanced up-converter mixer/modulator suppresses even harmonics.

Abstract translation: 用于发射机的增强极化调制器。 在锁相环（PLL）中，使用两点调制拓扑，其中相位信息通过限制器（例如，+ 90°或+ re / 2），其中相位信息动态范围除以因子 例如，通过2）和最大频率偏差也除以因子（例如，2）。 然后，实现双平衡上变频混频器/调制器来执行增益调整（例如，幅度和/或幅度调整）以及0°和+ 180°或0和+ re的相位变化（例如，负增益值可以是 就业）。 这种架构中的相位调整被分离并提供给发射机模块内的PLL和这种极性调制器的混频器/调制器，例如可以在通信设备（例如，其可以是无线通信设备）内实现。 这种包括具有双平衡上变频混频器/调制器的PLL的架构抑制了偶次谐波。

公开(公告)号：US20100141313A1

公开(公告)日：2010-06-10

申请号：US12330885

申请日：2008-12-09

Applicant: Jifeng Geng ,  Gary John Ballantyne ,  Daniel F. Filipovic

Inventor： Jifeng Geng ,  Gary John Ballantyne ,  Daniel F. Filipovic

IPC: H03L7/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0966

Abstract: A digital phase-locked loop (DPLL) supporting two-point modulation with adaptive delay matching is described. The DPLL includes highpass and lowpass modulation paths that support wideband and narrowband modulation, respectively, of the frequency and/or phase of an oscillator. The DPLL can adaptively adjust the delay of one modulation path to match the delay of the other modulation path. In one design, the DPLL includes an adaptive delay unit that provides a variable delay for one of the two modulation paths. Within the adaptive delay unit, a delay computation unit determines the variable delay based on a modulating signal applied to the two modulation paths and a phase error signal in the DPLL. An interpolator provides a fractional portion of the variable delay, and a programmable delay unit provides an integer portion of the variable delay.

Abstract translation: 描述了支持具有自适应延迟匹配的两点调制的数字锁相环（DPLL）。 DPLL包括分别支持振荡器的频率和/或相位的宽带和窄带调制的高通和低通调制路径。 DPLL可以自适应地调整一个调制路径的延迟以匹配另一个调制路径的延迟。 在一种设计中，DPLL包括为两个调制路径中的一个提供可变延迟的自适应延迟单元。 在自适应延迟单元内，延迟计算单元基于施加到两个调制路径的调制信号和DPLL中的相位误差信号来确定可变延迟。 内插器提供可变延迟的小数部分，并且可编程延迟单元提供可变延迟的整数部分。

公开(公告)号：US07706495B2

公开(公告)日：2010-04-27

申请号：US11078701

申请日：2005-03-14

Applicant: Shunsuke Hirano ,  Mamoru Arayashiki

Inventor： Shunsuke Hirano ,  Mamoru Arayashiki

IPC: H03D3/24

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

Abstract: A two-point frequency modulation apparatus is proposed whereby the spectrum of transmission waves is kept within the spectrum mask. Voltage is supplied to the control voltage terminal of VCO 1 in accordance with modulation data via noise shaper 101 that has operating characteristics of attenuating more noise at higher frequencies. As a result, by virtue of the working of noise shaper 101, the signal level outputted from the PLL circuit combining the modulation signal and the quantization noise decreases in proportion to the distance form the central frequency, so that two-point frequency modulation apparatus 100 is made possible whereby the spectrum of an RF modulation signal is kept within the spectrum mask.

Abstract translation: 提出了两点式调制装置，其中发射波的频谱保持在频谱掩模内。 电压根据调制数据通过噪声整形器101提供给VCO1的控制电压端，噪声整形器101具有在较高频率下衰减更多噪声的操作特性。 结果，通过噪声整形器101的工作，组合调制信号和量化噪声的PLL电路输出的信号电平与中心频率的距离成比例地减小，使得两点式调频装置100 使得RF调制信号的频谱保持在频谱掩模内。

公开(公告)号：US20100066459A1

公开(公告)日：2010-03-18

申请号：US12585319

申请日：2009-09-11

Applicant: Hyung-Ki Ahn

Inventor： Hyung-Ki Ahn

IPC: H03C3/06

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991

Abstract: A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.

Abstract translation: 提供了两点相位调制器和校准其转换增益的方法。 两点相位调制器通过在操作开始时在锁相环（PLL）电路中充电和抽取电荷来锁定输出频率信号，打开PLL电路的一个环路一段时间，并施加步进信号 ，从而校准控制输出频率信号的调制信号的转换增益。 因此，可以通过一次的校准操作来精确地校准转换增益。

公开(公告)号：US07579922B2

公开(公告)日：2009-08-25

申请号：US11471147

申请日：2006-06-20

Applicant: Henrik T. Jensen ,  Brima B. Ibrahim

Inventor： Henrik T. Jensen ,  Brima B. Ibrahim

IPC: H03C3/09

CPC classification number: H03L7/1976 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/095 ,  H03C3/0991 ,  H03L7/093

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

公开(公告)号：US07545865B2

公开(公告)日：2009-06-09

申请号：US10308593

申请日：2002-12-03

Applicant: David Bengtson

Inventor： David Bengtson

IPC: H04L27/00

CPC classification number: H03C3/0991 ,  H03C3/0925 ,  H03C3/0933

Abstract: An apparatus for electromagnetic processing comprises a modulator for generating one or more elements representative of an input signal; a divider controlled by the one or more elements and receiving an electromagnetic wave to generate a modified signal; a comparator for comparing the modified signal to a reference signal and for generating a processed signal based upon the comparison; and a channel number calculator for selecting a channel for the processed signal, wherein the input signal incorporated the channel selection.

Abstract translation: 一种用于电磁处理的装置包括用于产生表示输入信号的一个或多个元件的调制器; 由所述一个或多个元件控制的并且接收电磁波以产生修改信号的分频器; 比较器，用于将修改的信号与参考信号进行比较，并用于基于该比较产生处理的信号; 以及频道号计算器，用于选择处理信号的频道，其中输入信号包含频道选择。

公开(公告)号：US07532696B2

公开(公告)日：2009-05-12

申请号：US10991811

申请日：2004-11-18

Applicant: Patrick J. Pratt ,  Michael A. Milyard ,  Louis M. Nigra ,  Daniel B. Schartz

Inventor： Patrick J. Pratt ,  Michael A. Milyard ,  Louis M. Nigra ,  Daniel B. Schartz

IPC: H03D3/24

CPC classification number: H03C3/0991 ,  H03C3/0925 ,  H03C3/0933

Abstract: A calibration device for a phase locked loop arranged to generate an output frequency based upon a first frequency range of an input signal applied to a first input and a second frequency range of the input signal applied to a second input, the calibration phase locked loop synthesizer device comprising an estimator arranged to use a two dimensional estimation algorithm with a signal value indicative of a mismatch between the first input path and the second input path to determine an estimate of the mismatch to allow matching of the first input path and the second input path.

Abstract translation: 一种用于锁相环的校准装置，其被布置成基于施加到施加到第二输入的输入信号的第一输入的输入信号的第一频率范围和施加到第二输入的输入信号的第二频率范围产生输出频率，所述校准锁相环合成器 装置，包括估计器，被布置为使用具有指示第一输入路径和第二输入路径之间的失配的信号值的二维估计算法，以确定不匹配的估计，以允许第一输入路径和第二输入路径 。

公开(公告)号：US07508276B2

公开(公告)日：2009-03-24

申请号：US11785028

申请日：2007-04-13

Applicant: Sascha Beyer ,  Rolf Jaehne

Inventor： Sascha Beyer ,  Rolf Jaehne

IPC: H03L7/00

CPC classification number: H03C3/0925 ,  H03C3/0933 ,  H03C3/0941 ,  H03C3/0958

Abstract: A frequency modulator is provided for generating an output signal with a frequency that is a function of a modulation signal, wherein the modulation signal can assume N≧2 different discrete modulation values, and a predetermined frequency value of the output signal is associated with each modulation value, containing: a) a closed phase locked loop with a loop filter for providing a first control voltage, with a voltage controlled oscillator for generating the output signal, and with a switchable frequency divider for deriving a frequency-divided signal, and b) a modulation unit that is designed to provide, at a first output, values of a divisor that are a function of the modulation signal, and at a second output, a second control voltage that is a function of the modulation signal, c) wherein the oscillator has a first control input connected to the loop filter and has a second control input connected to the second output of the modulation unit, and is designed to generate the output signal as a function of the first control voltage and the second control voltage, d) and wherein the frequency divider is connected to the first output of the modulation unit and is designed to derive the frequency-divided signal in such a manner that it has instantaneous frequencies that are a function of the divisor values. According to the invention, the modulation unit has a capacitive voltage divider with a center tap and is designed to provide the second control voltage at the center tap. The invention further concerns a transmitting/receiving device and an integrated circuit having such a frequency modulator.

Abstract translation: 提供了一种频率调制器，用于产生具有调制信号的函数的频率的输出信号，其中调制信号可以采用N≥2个不同的离散调制值，并且输出信号的预定频率值与每个调制信号相关联 调制值，包括：a）具有用于提供第一控制电压的环路滤波器的闭合锁相环，具有用于产生输出信号的压控振荡器，以及用于导出分频信号的可切换分频器，b ）调制单元，其被设计为在第一输出处提供作为调制信号的函数的除数的值，并且在第二输出处提供作为调制信号的函数的第二控制电压，c）其中 所述振荡器具有连接到所述环路滤波器的第一控制输入端，并且具有连接到所述调制单元的第二输出的第二控制输入，并且被设计成产生所述输出 信号作为第一控制电压和第二控制电压的函数，d）并且其中分频器连接到调制单元的第一输出，并且被设计为导出分频信号，使得其具有瞬时 频率是除数值的函数。 根据本发明，调制单元具有带中心抽头的电容分压器，并被设计成在中心抽头提供第二控制电压。 本发明还涉及一种具有这种频率调制器的发射/接收装置和集成电路。

公开(公告)号：US07502435B2

公开(公告)日：2009-03-10

申请号：US10879431

申请日：2004-06-29

Applicant: Markus Hammes

Inventor： Markus Hammes

IPC: H03D3/24 ,  H03L7/08

CPC classification number: H03C3/095 ,  H03C3/0925 ,  H03C3/0933 ,  H03C3/0941

Abstract: The present invention provides a two-point modulator arrangement with a PLL that can be operated at various reference frequencies. A modulation signal provided by a digital signal processor is supplied as an analog signal at the input of the oscillator in the PLL and as a digital modulation signal on a frequency divider. For the purpose of pulse shaping the digital modulation data, a digital filter is provided that is coupled to the control input of the frequency divider and, in line with the principle proposed, is operated at the same, constant clock frequency as the signal processor, regardless of the reference frequency. As a result, no resynchronization of the digital modulation data is necessary upstream of the digital filter.

Abstract translation: 本发明提供一种具有可以在各种参考频率下工作的PLL的两点调制器装置。 由数字信号处理器提供的调制信号作为模拟信号提供在PLL中的振荡器的输入端，并作为分频器上的数字调制信号提供。 为了对数字调制数据进行脉冲整形，提供耦合到分频器的控制输入的数字滤波器，并且根据所提出的原理，以与信号处理器相同的恒定时钟频率操作， 无论参考频率如何。 因此，数字滤波器的上游不需要数字调制数据的再同步。