公开(公告)号：US20020043686A1

公开(公告)日：2002-04-18

申请号：US09878681

申请日：2001-06-11

发明人： Ronald J. Bolam ,  Subhash B. Kulkarni ,  Dominic J. Schepis

IPC分类号： H01L021/78 ,  H01L021/46 ,  H01L021/301 ,  H01L021/76 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66772 ,  H01L21/743 ,  H01L21/76264 ,  H01L21/76283 ,  H01L27/1203 ,  H01L29/78636 ,  H01L29/78648

摘要： An SOI chip having an isolation barrier. The SOI chip includes a substrate, an oxide layer deposited on the substrate, and a silicon layer deposited on the oxide layer. A gate is deposited above the silicon layer. A first metal contact is deposited above the gate to form an electrical contact with the gate. Second and third metal contacts are deposited to form electrical contacts with the silicon layer. The isolation barrier extends through the silicon layer and the oxide layer, and partially into the substrate, to block impurities in the oxide layer outside the isolation barrier from diffusing into the oxide layer inside the isolation barrier. The isolation barrier surrounds the gate, the first metal contact, the second metal contact, and the third metal contactnullwhich define an active chip area inside the isolation barrier. A method of manufacturing the SOI chip is also disclosed.

摘要翻译： 具有隔离屏障的SOI芯片。 SOI芯片包括衬底，沉积在衬底上的氧化物层和沉积在氧化物层上的硅层。 栅极沉积在硅层上方。 第一金属触点沉积在栅极上方以形成与栅极的电接触。 沉积第二和第三金属触点以形成与硅层的电接触。 隔离屏障延伸穿过硅层和氧化物层，并部分地延伸到衬底中，以阻挡隔离屏障之外的氧化物层中的杂质扩散到隔离屏障内部的氧化物层中。 隔离屏障围绕栅极，第一金属触点，第二金属触点和第三金属触点，其限定隔离屏障内部的有源芯片区域。 还公开了制造SOI芯片的方法。

公开(公告)号：US20020033505A1

公开(公告)日：2002-03-21

申请号：US09939748

申请日：2001-08-28

申请人： Hitachi, Ltd.

发明人： Hiroshi Kujirai ,  Masahiro Moniwa

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L27/10894 ,  H01L21/823814 ,  H01L27/0921 ,  H01L27/10814 ,  H01L27/10873

摘要： In order to provide a technique to restrain the punch-through phenomenon of an MISFET constituting a memory cell or the like of a DRAM and to improve the retention time of the memory cell of the DRAM, a threshold value regulating impurity regions SA3 is formed, for example, by implanting BF ions, in a semiconductor substrate under a p-type gate electrode 9p of an information transferring MISFET Qs of the DRAM, and a punch-through preventing region PA is formed to cover end portions of the source and the drain of the information transferring MISFET Qs at a position deeper than the threshold value regulating impurity regions SA3 by implanting an impurity including an atom whose weight is heavier than that of the threshold value regulating impurity atom, for example, In.

摘要翻译： 为了提供一种限制构成DRAM的存储单元等的MISFET的穿透现象并提高DRAM的存储单元的保持时间的技术，形成了调节杂质区SA3的阈值， 例如通过将MAG离子注入到DRAM的信息传递MISFET Qs的p型栅电极9p下方的半导体衬底中，并且形成穿通防止区域PA以覆盖源极和漏极的端部 通过注入包含重量比限制杂质原子的阈值的重量的原子的杂质（例如In），在比通过调节杂质区域SA3的阈值更深的位置处传送MISFET Qs的信息。

公开(公告)号：US20020017689A1

公开(公告)日：2002-02-14

申请号：US09778104

申请日：2001-01-07

申请人： MITSUBISHI DENKI KABUSHIKI KAISHA

发明人： Yuuichi Hirano ,  Shigenobu Maeda ,  Shigeto Maegawa

IPC分类号： H01L027/01 ,  H01L027/12

CPC分类号： H01L29/6653 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0692 ,  H01L29/41758 ,  H01L29/42384 ,  H01L29/66575 ,  H01L29/7833 ,  H01L29/7836 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a manufacturing method thereof are obtained which can restrain increase of the parasitic capacitance generated between contact plugs of source/drain regions and a gate electrode while reducing the area of the source/drain regions. A channel region is formed under a gate electrode 1. A pair of source/drain regions 2 are formed to sandwich the channel region. The source/drain regions 2 have a first part 3a being adjacent to the channel region and a second part 3b formed to protrude in a channel width direction from the first part 3a so that a part of outer peripheries of the source/drain regions 2 extend away from the gate electrode 1 in a plan view. Contact plugs 4 are formed on the second part 3b for connecting the source/drain regions 2 to source/drain wirings.

摘要翻译： 获得半导体器件及其制造方法，其可以抑制在源极/漏极区域的接触插塞与栅极电极之间产生的寄生电容的增加，同时减小源极/漏极区域的面积。 沟道区域形成在栅极电极1的下方。形成一对源极/漏极区域2以夹持沟道区域。 源极/漏极区域2具有与沟道区域相邻的第一部分3a和形成为从第一部分3a沿沟道宽度方向突出的第二部分3b，使得源极/漏极区域2的外周的一部分延伸 在平面图中远离栅电极1。 接触插塞4形成在第二部分3b上，用于将源极/漏极区域2连接到源极/漏极布线。

公开(公告)号：US20020017665A1

公开(公告)日：2002-02-14

申请号：US09978050

申请日：2001-10-17

申请人： LG Electronics, Inc.

发明人： Ki-Hyun Lyu ,  Kwang-Jo Hwang

IPC分类号： H01L021/00 ,  H01L021/84 ,  H01L029/76 ,  H01L029/94 ,  H01L031/062 ,  H01L031/113 ,  H01L031/119 ,  H01L027/108 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/3205 ,  H01L021/4763

CPC分类号： H01L27/12 ,  H01L29/4908

摘要： A thin film transistor is disclosed, including an insulating substrate, a semiconductor layer formed on the insulating substrate, the semiconductor layer having an active region and an impurity region, a gate insulating layer formed on the active region of the semiconductor layer, a first gate metal layer formed on a predetermined portion of the active region of the semiconductor layer to define a channel region, and a second gate metal layer formed on the first gate metal layer. The first and second gate metal layers have different compositions, such that the second gate metal layer etches faster than the first gate metal layer, thereby preventing formation of a hillock. A first protective layer is formed over the structure, then a light shielding layer, and then a second protective layer is formed over the light shielding layer.

摘要翻译： 公开了一种薄膜晶体管，其包括绝缘基板，形成在绝缘基板上的半导体层，具有有源区和杂质区的半导体层，形成在半导体层的有源区上的栅极绝缘层，第一栅极 金属层形成在半导体层的有源区的预定部分上以限定沟道区，以及形成在第一栅极金属层上的第二栅极金属层。 第一和第二栅极金属层具有不同的组成，使得第二栅极金属层比第一栅极金属层蚀刻更快，从而防止形成小丘。 在结构上形成第一保护层，然后在遮光层上形成遮光层，然后形成第二保护层。

公开(公告)号：US20020014664A1

公开(公告)日：2002-02-07

申请号：US09895159

申请日：2001-07-02

发明人： Jack A. Mandelman ,  Edward J. Nowak ,  William R. Tonti

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/7302 ,  H01L21/84 ,  H01L27/1203

摘要： A multi-function semiconductor device is provided. The device includes a bipolar transistor and an FET formed in parallel. A semiconductor substrate is provided on an insulating layer. A source/emitter region and a drain region are formed in the semiconductor substrate and border first opposite sides of a body region therebetween. A gate is formed above the substrate between the source/emitter region and the drain region to form an FET having three terminals including the gate, the source/emitter region, and the drain region. A collector region is formed in the substrate abutting the drain region and extending further under the gate and the drain region. A bipolar transistor having three terminals is formed including a base region, the source/emitter, and the collector region. A shortest distance between the collector region and the source/emitter region defines a base width.

摘要翻译： 提供了多功能半导体器件。 该器件包括并联形成的双极晶体管和FET。 半导体衬底设置在绝缘层上。 源极/发射极区域和漏极区域形成在半导体衬底中并且与其间的体区域的第一相对侧边界。 在源极/发射极区域和漏极区域之间的衬底上方形成栅极，以形成具有包括栅极，源极/发射极区域和漏极区域的三个端子的FET。 集电极区域形成在与衬底邻接的衬底中，并在栅极和漏极区域之下进一步延伸。 形成具有三个端子的双极晶体管，其包括基极区域，源极/发射极和集电极区域。 集电极区域和源极/发射极区域之间的最短距离定义基极宽度。

公开(公告)号：US20020014661A1

公开(公告)日：2002-02-07

申请号：US09735476

申请日：2000-12-14

申请人： FUJITSU LIMITED

发明人： Tadahiro Okamoto ,  Hirohisa Matsuki

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68363 ,  H01L2924/0002 ,  H01L2924/00

摘要： A plurality of chips divided from a semiconductor wafer having a plurality of semiconductor integrated circuits formed on a front surface of the wafer, are prepared, front surfaces of the chips being bonded to a first wafer sheet. The back and side surfaces of each chip bonded to the first wafer sheet are covered with a reinforcing thin film. Each of the plurality of chips is removed from the first wafer sheet. The flexural strength of a chip can be suppressed from being lowered by chipping and chip cracks.

摘要翻译： 制备从形成在晶片前表面上的具有多个半导体集成电路的半导体晶片分开的多个芯片，芯片的前表面被接合到第一晶片。 结合到第一晶片片的每个芯片的背面和侧表面被增强薄膜覆盖。 将多个芯片中的每一个从第一晶片片上移除。 可以抑制芯片的弯曲强度由于切屑和芯片裂纹而降低。

公开(公告)号：US20020009824A1

公开(公告)日：2002-01-24

申请号：US09768233

申请日：2001-01-25

申请人： Mitsubishi Denki Kabushiki Kaisha

发明人： Atsushi Maeda

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  H01L021/00

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14643 ,  H01L27/14689

摘要： In a semiconductor device having a solid state image sensing device of the present invention, a p-type well region 2a in which a plurality of unit cells, each having a photodiode PD, are formed and a p-type well region 2b in which a peripheral circuit element is formed are installed in a separated manner. Thus, it is possible to prevent a hot carrier, transition metals, etc. within the peripheral circuit region from invading the pixel region more effectively. Consequently, it becomes possible to provide a semiconductor device having a solid state image sensing device and a manufacturing method thereof, which can improve the pixel characteristic.

摘要翻译： 在具有本发明的固态摄像装置的半导体装置中，形成有多个具有光电二极管PD的单位电池的p型阱区域2a和p型阱区域2b，其中， 外围电路元件形成为分离的方式安装。 因此，可以防止外围电路区域内的热载流子，过渡金属等更有效地侵入像素区域。 因此，可以提供一种能够提高像素特性的具有固体摄像装置及其制造方法的半导体装置。

公开(公告)号：US20020008283A1

公开(公告)日：2002-01-24

申请号：US09477067

申请日：2000-01-03

发明人： DONG-HYUK JU

IPC分类号： H01L031/0392 ,  H01L027/12 ,  H01L027/01

CPC分类号： H01L27/1203 ,  H01L21/76224

摘要： In one embodiment, the present invention relates to a method of forming a Silicon-on-Insulator substrate involving providing a structure comprising a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer, and a mask layer over the silicon device layer; etching portions of the mask layer, the silicon device layer, and the buried insulation layer thereby forming openings and exposing portions of the bulk silicon layer; depositing polysilicon in the openings; removing a portion of the polysilicon in the openings to form polysilicon sidewalls adjacent the silicon device layer and the buried insulation layer and to form gaps at least partially surrounded by the polysilicon sidewalls; depositing an insulation material in the gaps; and removing the mask layer. In another embodiment, the present invention relates to a Silicon-on-Insulator substrate made of a bulk silicon layer, a buried insulation layer over the bulk silicon layer, a silicon device layer over the buried insulation layer; a plurality of at least one of holes and trenches in the silicon device layer and the buried insulation layer, wherein the plurality of at least one of holes and trenches contains a polysilicon sidewall adjacent the bulk silicon layer, the buried insulation layer, and the silicon device layer, the polysilicon sidewall surrounding an insulating material, the insulating material in contact with the bulk silicon layer.

摘要翻译： 在一个实施例中，本发明涉及一种形成绝缘体上硅绝缘体衬底的方法，其包括提供包括体硅层，体硅层上的掩埋绝缘层，掩埋绝缘层上的硅器件层的结构， 以及在硅器件层上的掩模层; 蚀刻掩模层，硅器件层和掩埋绝缘层的部分，从而形成开孔并暴露体硅层的部分; 在开口中沉积多晶硅; 去除所述开口中的所述多晶硅的一部分以形成邻近所述硅器件层和所述掩埋绝缘层的多晶硅侧壁，并形成至少部分被所述多晶硅侧壁包围的间隙; 在间隙中沉积绝缘材料; 并去除掩模层。 在另一个实施例中，本发明涉及一种由体硅层制成的绝缘体上硅绝缘体，该体硅层上的掩埋绝缘层，该掩埋绝缘层上的硅器件层; 所述硅器件层和所述掩埋绝缘层中的多个至少一个孔和沟槽，其中所述多个至少一个孔和沟槽包含邻近所述体硅层的多晶硅侧壁，所述掩埋绝缘层和所述硅 器件层，围绕绝缘材料的多晶硅侧壁，绝缘材料与体硅层接触。

公开(公告)号：US20020005540A1

公开(公告)日：2002-01-17

申请号：US09742090

申请日：2000-12-22

发明人： Dong Hee Kim ,  Kyo Ho Moon

IPC分类号： H01L027/108 ,  H01L029/76 ,  H01L029/94 ,  H01L031/119 ,  H01L029/04 ,  H01L031/036 ,  H01L027/01 ,  H01L027/12 ,  H01L031/0392

CPC分类号： H01L29/66765 ,  H01L27/12

摘要： A thin film transistor and a fabricating method thereof are adaptive for increasing a capacitance of a storage capacitor. In the method, a gate electrode and a lower electrode of a capacitor are formed at the transistor area and the capacitor area of an insulating substrate, respectively. A gate insulating film, an active layer and an ohmic contact layer on the insulating substrate is sequentially formed to cover the gate electrode and the lower electrode. The ohmic contact layer and the active layer are primarily patterned in such a manner as to be left only at a portion corresponding to the gate electrode of the transistor area and thus expose the gate insulating film. Then, the ohmic contact layer and the active layer are secondarily patterned in such a manner as to reduce the thickness of the gate insulating film at a portion corresponding to the lower electrode. The source and drain electrodes are formed on the gate insulating film at the transistor area, and an upper electrode of the capacitor is formed at a portion corresponding to the lower electrode on the gate insulating film of the capacitor.

公开(公告)号：US20020003260A1

公开(公告)日：2002-01-10

申请号：US09865475

申请日：2001-05-29

发明人： Norio Murakami

IPC分类号： H01L027/01 ,  H01L027/12 ,  H01L031/0392 ,  C30B001/00 ,  H01L021/20 ,  H01L021/36 ,  H01L021/425

CPC分类号： H01L29/66787 ,  H01L29/7834

摘要： To present a SOI type MOS element excellent in yield, performance and characteristic, easy in manufacture, and low in cost, and a method of manufacturing the same. A SOI type MOS transistor structure comprising polysilicon electrodes 128 for gate, source and drain composed by burying into trench holes 120a, 120b, 120c respectively formed in a semiconductor substrate 110, a gate oxide film 122 formed in the entire inside of the trench hole 120a, N-diffusion layer 124 and Nnull diffusion layer 126 formed in the entire inside of the trench holes 120b and 120c, and a thick SiO2 film 114 in a trench hole 113 formed in the semiconductor substrate 110 so as to surround the transistor.

摘要翻译： 为了表现出良好的产率，性能和特性，易于制造和成本低的SOI型MOS元件及其制造方法。 一种SOI型MOS晶体管结构，包括通过埋入分别形成在半导体衬底110中的沟槽120a，120b，120c中的栅极，源极和漏极的多晶硅电极128，形成在沟槽120a的整个内部的栅极氧化膜122 形成在沟槽120b和120c的整个内部的N扩散层124和N +扩散层126以及形成在半导体衬底110中以围绕晶体管的沟槽113中的厚SiO 2膜114。