公开(公告)号：US10114767B2

公开(公告)日：2018-10-30

申请号：US13837822

申请日：2013-03-15

申请人： Intel Corporation

发明人： Steven M. Bennett ,  Andrew V. Anderson ,  Gilbert Neiger ,  Rajesh Sankaran Madukkarumukumana ,  Richard UhligQ ,  Lawrence Smith, III ,  Scott D. Rodgers

IPC分类号： G06F12/10 ,  G06F12/14 ,  G06F9/455 ,  G06F12/109

摘要： A processor including a virtualization system of the processor with a memory virtualization support system to map a reference to guest-physical memory made by guest software executable on a virtual machine which in turn is executable on a host machine in which the processor is operable to a reference to host-physical memory of the host machine.

公开(公告)号：US10102145B1

公开(公告)日：2018-10-16

申请号：US14961762

申请日：2015-12-07

申请人： Seagate Technology LLC

发明人： Richard P Michel ,  Mark A Gaertner ,  Kevin Nghia Dao

IPC分类号： G06F12/109 ,  G06F3/06 ,  G06F11/10

摘要： Systems and methods are disclosed to perform out of order LBA processing at a data storage device. A data storage device may be configured to receive a read command including a sequential LBA range, read data for the LBA range in non-sequential order and store the data to a buffer, and return the data to the host in sequential LBA order. The storage device may begin a read operation at a sector in the middle of the LBA range, and read the beginning of the LBA range on a next rotation of the media. The storage device may note the location of read errors without interrupting a read operation. Successfully read data may be buffered, while rereads and error recovery may be performed only on LBAs at which errors were encountered. Once the data from the LBA range has been acquired, the data may be organized into sequential order.

公开(公告)号：US10089033B2

公开(公告)日：2018-10-02

申请号：US15122533

申请日：2014-04-24

申请人： HITACHI, LTD.

发明人： Akira Yamamoto ,  Junji Ogawa ,  Norio Shimozono ,  Yoshihiro Yoshii ,  Kazuei Hironaka ,  Atsushi Kawamura

IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F3/06 ,  G06F12/084 ,  G06F12/0866 ,  G06F12/0871 ,  G06F12/0873 ,  G06F12/1009 ,  G06F12/109 ,  G06F12/02 ,  G06F11/10 ,  G06F17/30

摘要： A storage system according to the present invention has a plurality of flash packages equipped with a deduplication function. When a storage controller transmits a write data and a feature value of write data to a flash package, the flash package compares contents of the write data with data having a same feature value as the feature value of the write data. As a result of the comparison, if there is no corresponding data, the write data is stored in the flash memory, but if there is a corresponding data, the new data will not be stored. Thus, a greater number of data can be stored in the flash memory while preventing deterioration of performance.

公开(公告)号：US10037280B2

公开(公告)日：2018-07-31

申请号：US14726454

申请日：2015-05-29

申请人： QUALCOMM Incorporated

发明人： Jason Edward Podaima ,  Paul Christopher John Wiercienski ,  Kyle John Ernewein ,  Carlos Javier Moreira ,  Meghal Varia ,  Serag Gadelrab ,  Muhammad Umar Choudry

IPC分类号： G06F12/08 ,  G06F12/10 ,  G06F12/0862 ,  G06F12/109

CPC分类号： G06F12/0862 ,  G06F12/10 ,  G06F12/109 ,  G06F2212/1021 ,  G06F2212/283 ,  G06F2212/312 ,  G06F2212/507 ,  G06F2212/6026 ,  G06F2212/608 ,  G06F2212/65 ,  G06F2212/654

摘要： Systems and methods for pre-fetching address translations in a memory management unit (MMU) are disclosed. The MMU detects a triggering condition related to one or more translation caches associated with the MMU, the triggering condition associated with a trigger address, generates a sequence descriptor describing a sequence of address translations to pre-fetch into the one or more translation caches, the sequence of address translations comprising a plurality of address translations corresponding to a plurality of address ranges adjacent to an address range containing the trigger address, and issues an address translation request to the one or more translation caches for each of the plurality of address translations, wherein the one or more translation caches pre-fetch at least one address translation of the plurality of address translations into the one or more translation caches when the at least one address translation is not present in the one or more translation caches.

公开(公告)号：US20180157595A1

公开(公告)日：2018-06-07

申请号：US15366251

申请日：2016-12-01

申请人： Ampere Computing LLC

发明人： Ankit Jindal ,  Pranavkumar Sawargaonkar ,  Keyur Chudgar

IPC分类号： G06F12/1009 ,  G06F3/06 ,  G06F12/109

CPC分类号： G06F12/1009 ,  G06F3/061 ,  G06F3/064 ,  G06F3/0664 ,  G06F3/067 ,  G06F12/109 ,  G06F12/1425 ,  G06F2212/1016 ,  G06F2212/1024 ,  G06F2212/152 ,  G06F2212/154

摘要： Various aspects provide for optimizing memory mappings associated with network nodes. For example, a system can include a first network node and a second network node. The first network node generates a memory page request in response to an invalid memory access associated with a virtual central processing unit of the first network node. The second network node receives the memory page request in response to a determination that the second network node comprises a memory space associated with the memory page request. The first network node also maps a memory page associated with the memory page request based on a set of memory page mappings stored by the first network node.

公开(公告)号：US09971705B2

公开(公告)日：2018-05-15

申请号：US15048400

申请日：2016-02-19

申请人： Intel Corporation

发明人： Gur Hildesheim ,  Shlomo Raikin ,  Ittai Anati ,  Gideon Gerzon ,  Uday Savagaonkar ,  Francis Mckeen ,  Carlos Rozas ,  Michael Goldsmith ,  Prashant Dewan

IPC分类号： G06F12/10 ,  G06F12/109 ,  G06F12/1036 ,  G06F12/02

CPC分类号： G06F12/109 ,  G06F12/0284 ,  G06F12/1036 ,  G06F2212/656 ,  G06F2212/657

摘要： Embodiments of apparatuses and methods including virtual address memory range registers are disclosed. In one embodiment, a processor includes a memory interface, address translation hardware, and virtual memory address comparison hardware. The memory interface is to access a system memory using a physical memory address. The address translation hardware is to support translation of a virtual memory address to the physical memory address. The virtual memory address is used by software to access a virtual memory location in the virtual memory address space of the processor. The virtual memory address comparison hardware is to determine whether the virtual memory address is within a virtual memory address range.

公开(公告)号：US09898274B2

公开(公告)日：2018-02-20

申请号：US14987074

申请日：2016-01-04

申请人： International Business Machines Corporation

发明人： Andre L. Albot ,  Vishal C. Aslot ,  Thomas V. Burks, III ,  John D. Dietel

IPC分类号： G06F9/44 ,  G06F9/445 ,  G06F13/16 ,  G06F13/24 ,  G06F12/109 ,  G06F12/10 ,  G06F13/42

CPC分类号： G06F8/65 ,  G06F8/654 ,  G06F12/10 ,  G06F12/109 ,  G06F13/1668 ,  G06F13/24 ,  G06F13/4282 ,  G06F2212/657 ,  G06F2213/2424

摘要： The present disclosure relates to updating a firmware image on a coherent hardware accelerator concurrently with executing operations on the coherent hardware accelerator. According to one embodiment, while executing accelerator-enabled operations on the coherent hardware accelerator, a system stores a firmware update package in a local memory on the coherent hardware accelerator. Once the firmware update package is stored in local memory on the coherent hardware accelerator, the system restarting the coherent hardware accelerator by pausing the execution of at least a first operation initiated on the coherent hardware accelerator and applying the firmware update package to the firmware image on the coherent hardware accelerator. Once the firmware update package is applied to the coherent hardware accelerator, the system resumes the operation on the coherent hardware accelerator.

公开(公告)号：US20180018273A1

公开(公告)日：2018-01-18

申请号：US15210348

申请日：2016-07-14

申请人： International Business Machines Corporation

发明人： Ramanjaneya S. Burugula ,  Niteesh K. Dubey ,  Joefon Jann ,  Pratap C. Pattnaik ,  Hao Yu

IPC分类号： G06F12/109

CPC分类号： G06F12/109 ,  G06F9/50 ,  G06F2212/1008 ,  G06F2212/1041 ,  G06F2212/657

摘要： A server LPAR operating in a virtualized computer shares pages with client LPARs using a shared memory region (SMR). A virtualization function of the computer receives a get-page-ID request associated with a client LPAR to identify a physical page corresponding to a shared page included in the SMR. The virtualization function requests the server LPAR to provide an identity of the physical page. The virtualization function receives a page-ID response comprising the identity of a server LPAR logical page that corresponds to the physical page. The virtualization element determines a physical page identity and communicates the physical page identity to the client LPAR. The virtualization element receives a page ID enter request and enters an identity of the physical page into a translation element of the computer to associate a client LPAR logical page with the physical page.

公开(公告)号：US09858184B2

公开(公告)日：2018-01-02

申请号：US14840829

申请日：2015-08-31

申请人： International Business Machines Corporation

发明人： Gheorghe Almasi ,  Hubertus Franke ,  Gokul B. Kandiraju ,  Davide Pasetto ,  Hartmut Penner

IPC分类号： G06F12/00 ,  G06F12/06 ,  G06F3/06 ,  G06F12/109 ,  G06F13/16 ,  G06F9/50 ,  G06F21/78

CPC分类号： G06F12/0646 ,  G06F3/06 ,  G06F9/50 ,  G06F12/109 ,  G06F13/16 ,  G06F21/78 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/657

摘要： A method, system and computer program product are disclosed for direct storage device sharing in a virtualized environment. In an embodiment, the method comprises assigning each of a plurality of virtual functions an associated memory area of a physical memory, and executing the virtual functions in a single root-input/output virtualization environment to provide each of a plurality of guests with direct access to the physical memory. In one embodiment, each of the guests is associated with a respective one of the virtual functions; and the assigning each of the plurality of virtual functions an associated memory area includes maintaining a per-virtual function mapping table identifying a respective one mapping function for each of the virtual functions, and each of the mapping functions mapping one of the memory areas of the physical area to an associated virtual memory.

公开(公告)号：US20170344312A1

公开(公告)日：2017-11-30

申请号：US15448667

申请日：2017-03-03

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： JUNG-MIN SEO

IPC分类号： G06F3/06 ,  G06F12/109 ,  G06F12/0871 ,  G06F11/10

CPC分类号： G06F3/0689 ,  G06F3/061 ,  G06F3/0638 ,  G06F3/0644 ,  G06F3/0647 ,  G06F3/0665 ,  G06F11/102 ,  G06F11/1076 ,  G06F12/0871 ,  G06F12/109 ,  G06F2211/1004 ,  G06F2211/1009 ,  G06F2212/262

摘要： A storage system includes a plurality of storage media and a method of managing volumes of the storage system is applied thereto. The method includes receiving a volume management request and correlation information between the volumes, and allocating storage spaces of the storage media to the volumes based on the correlation information between the volumes. The correlation information indicates information of the volumes in which the allocated storage media are physically isolated from each other.