公开(公告)号：US4964142A

公开(公告)日：1990-10-16

申请号：US72955

申请日：1987-07-15

Applicant: Kadiresan Annamalai

Inventor： Kadiresan Annamalai

IPC: H04L7/00 ,  H04J3/06

CPC classification number: H04J3/0632

Abstract: Method and apparatus suited for use with a decoder receiving data serially from a network is disclosed providing synchronization throughout reception and decoding of packets of symbols. An appropriately-delayed read pointer initialization strobe used by an elastic buffer portion of the receiver provides the sequence of synchronization signals which avoids deletion of bits of packet preamble.

公开(公告)号：US4617478A

公开(公告)日：1986-10-14

申请号：US530176

申请日：1983-09-07

Applicant: Hemmige D. Varadarajan

Inventor： Hemmige D. Varadarajan

IPC: H03K17/04 ,  H03K17/60 ,  H03K19/013 ,  H03K19/086 ,  H03K19/082 ,  H03K19/092

CPC classification number: H03K19/086 ,  H03K19/013

Abstract: In accordance with the invention, the reference portion of a primitive current switch used in emitter coupled logic or current mode logic is modified by introducing a slow device as the reference element in order to enhance the speed of turn on and turn off of the input elements. In particular, the reference transistor of a conventional ECL inverter gate or conventional CML inverter gate is replaced with a slow transistor or slow diode in order to bypass the emitter dynamic resistance. The emitter time constant of the reference element Q.sub.R is thereby increased so that the voltage on the common current source node (node 3) does not change substantially when the base of the input elements change transiently. As a consequence, the collector output of the input element, such as transistor Q.sub.A is switched on or off significantly faster.

Abstract translation: 根据本发明，在发射极耦合逻辑或电流模式逻辑中使用的原始电流开关的参考部分通过引入一个慢速装置作为参考元件来修改，以增强输入元件的导通和关断速度 。 特别地，传统的ECL逆变器栅极或常规CML反相器栅极的参考晶体管被替换为慢晶体管或慢二极管，以便绕过发射极动态电阻。 因此，参考元件QR的发射极时间常数增加，使得当输入元件的基极瞬时变化时，公共电流源节点（节点3）上的电压基本上不变化。 因此，诸如晶体管QA的输入元件的集电极输出明显更快地被接通或断开。

公开(公告)号：US12254527B2

公开(公告)日：2025-03-18

申请号：US16879991

申请日：2020-05-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Timour T. Paltashev ,  Michael Mantor ,  Rex Eldon McCrary

IPC: G06T1/20 ,  G06T1/60 ,  G06T15/00 ,  G06T15/80 ,  G06T17/10

Abstract: A graphics processing unit (GPU) includes a plurality of programmable processing cores configured to process graphics primitives and corresponding data and a plurality of fixed-function hardware units. The plurality of processing cores and the plurality of fixed-function hardware units are configured to implement a configurable number of virtual pipelines to concurrently process different command flows. Each virtual pipeline includes a configurable number of fragments and an operational state of each virtual pipeline is specified by a different context. The configurable number of virtual pipelines can be modified from a first number to a second number that is different than the first number. An emulation of a fixed-function hardware unit can be instantiated on one or more of the graphics processing cores in response to detection of a bottleneck in a fixed-function hardware unit. One or more of the virtual pipelines can then be reconfigured to utilize the emulation instead of the fixed-function hardware unit.

公开(公告)号：US20250088193A1

公开(公告)日：2025-03-13

申请号：US18466221

申请日：2023-09-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Srikanth Reddy Gruddanti ,  Debasish Dwibedy ,  Manoj N. Kulkarni ,  Prasant Kumar Vallur ,  Priyadarshi Saxena

IPC: H03L7/081 ,  G06F1/04 ,  H03K3/011

Abstract: A method for driver calibration in die-to-die interfaces can include calibrating a delay lock loop of a delay line unit cell, by at least one processor, based on drive and load conditions of one or more driver unit cells of a physical layer of a die-to-die interconnect. The method can additionally include generating a clock signal, by the at least one processor, based on the delay lock loop. The method can further include communicating data, by the at least one processor, over the die-to-die interconnect based on the clock signal. Various other methods and systems are also disclosed.

公开(公告)号：US20250085848A1

公开(公告)日：2025-03-13

申请号：US18888463

申请日：2024-09-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Vydhyanathan KALYANASUNDHARAM

IPC: G06F3/06

Abstract: Systems, methods, and techniques are provided for a fabric addressable memory. A memory access request is received from a host computing device attached via one edge port of one or more interconnect switches, the memory access request directed to a destination segment of a physical fabric memory block that is allocated in local physical memory of the host computing device. The edge port accesses a stored mapping between segments of the physical fabric memory block and one or more destination port identifiers that are each associated with a respective edge port of the fabric addressable memory. The memory access request is routed by the one edge port to a destination edge port based on the stored mapping.

公开(公告)号：US12250493B2

公开(公告)日：2025-03-11

申请号：US18323789

申请日：2023-05-25

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Roto Le

IPC: H04N7/15 ,  G06F3/04842 ,  G06V10/22 ,  G06V20/40 ,  H04L65/403 ,  G06N20/00

Abstract: Machine learning-based multi-view video conferencing from single view video data, including: identifying, in video data, a plurality of objects; and generating a user interface comprising a plurality of first user interface elements each comprising a portion of the video data corresponding to one or more of the plurality of objects.

公开(公告)号：US20250070031A1

公开(公告)日：2025-02-27

申请号：US18944757

申请日：2024-11-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gabriel H LOH ,  Raja SWAMINATHAN ,  Rahul AGARWAL ,  Brett P. WILKERSON

IPC: H01L23/538 ,  G05F1/575 ,  H01L25/065 ,  H01L27/06

Abstract: A semiconductor package includes a package substrate having a first surface and an opposing second surface, and further includes an integrated circuit (IC) die disposed at the second surface and having a third surface facing the second surface and an opposing fourth surface. The IC die has a first region comprising one or more metal layers and circuit components for one or more functions of the IC die and a second region offset from the first region in a direction parallel with the third and fourth surfaces. The semiconductor package further includes a voltage regulator disposed at the fourth surface in the second region and having an input configured to receive a supply voltage and an output configured to provide a regulated voltage, and also includes a conductive path coupling the output of the voltage regulator to a voltage input of circuitry of the IC die.

公开(公告)号：US12236555B2

公开(公告)日：2025-02-25

申请号：US17561267

申请日：2021-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Linwei Yu ,  Jiangli Ye ,  Yang Ling ,  Hui Zhou

IPC: G06T3/4015 ,  G06T11/00 ,  G06V10/56

Abstract: A method and processing device for image demosaicing is provided. The processing device comprises memory and a processor. The processor is configured to, for a pixel of a Bayer image which filters an acquired image using three color components, determine directional color difference weightings in a horizontal direction and a vertical direction, determine a color difference between the first color component and the second color component and a color difference between the second color component and the third color component based on the directional color difference weightings, interpolate a color value of the pixel from the one color component and the color differences and provide a color image for display.

公开(公告)号：US12236109B2

公开(公告)日：2025-02-25

申请号：US18201696

申请日：2023-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Pratik Mishra ,  Sergey Blagodurov ,  Atul Kumar Sujayendra Sandur

IPC: G06F3/06 ,  G06F9/48 ,  G06F9/50

Abstract: A cloud computing system includes cloud orchestrator circuitry and fabric manager circuitry. The cloud orchestrator circuitry receives an input application and determines a task graph, a data graph, and a function popularity heap parameter for the input application. The task graph comprises an indication of function interdependency of functions of the input application, the data graph comprises an indication of data interdependency of the functions, and the function popularity heap parameter corresponds to a re-usability index for the functions. The fabric manager circuitry allocate a first programmable integrated circuit (IC) device to perform a first function of the input application based on the task graph, the data graph, and the function popularity heap parameter.

公开(公告)号：US20250044966A1

公开(公告)日：2025-02-06

申请号：US18362796

申请日：2023-07-31

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Nicholas Carmine DeFiore ,  Sridhar Varadharajulu Gada ,  James R. Magro ,  Michael L. Choate ,  Wayne Paul Rodrigue ,  NrusimhaVamsi Krishna Godavarti ,  Robert Gentile ,  Roozbeh Paribakht ,  Anwar Kashem

IPC: G06F3/06

Abstract: The disclosed device includes a cache that stores sets of settings for memory states, and registers that store a current set of settings for a memory. The device also includes a control circuit that can read, from the cache in response to the memory transitioning to a new memory state, a new set of settings corresponding to the new memory state, and write, to the plurality of registers, the new set of settings. Various other methods, systems, and computer-readable media are also disclosed.