公开(公告)号：US5878247A

公开(公告)日：1999-03-02

申请号：US899597

申请日：1997-07-24

申请人： Dong-Soo Cho

发明人： Dong-Soo Cho

IPC分类号： G06F11/22 ,  G06F3/00 ,  G06F11/14 ,  G06F11/26 ,  G06F11/28

CPC分类号： G06F11/1461 ,  G06F11/261

摘要： An improved automatic data backup apparatus for a microcomputer capable of automatically backing up a user's program at a central processing unit(CPU), which includes a central processing unit(CPU) for performing a user program and a monitor program outputted from a first emulator input/output circuit and a data/address bus; a second emulator input/output circuit for outputting a register signal applied thereto and for inputting/outputting a data between a register data bus connected to an emulator and a backup register bus; and a data backup storing circuit for automatically backing up a data stored in a register of the CPU corresponding to a user program performed in the CPU in accordance with a monitor program request signal outputted from the second emulator input/output circuit, a register signal, a register recording signal, and a register judgement signal and for applying a data stored in a register in the CPU corresponding to a user program which is changed by a backed-up monitor program.

摘要翻译： 一种用于能够在中央处理单元（CPU）处自动备份用户程序的微型计算机的自动数据备份装置，其包括用于执行用户程序的中央处理单元（CPU）和从第一仿真器输入输出的监视程序 /输出电路和数据/地址总线; 用于输出施加到其上的寄存器信号并用于在连接到仿真器的寄存器数据总线与备用寄存器总线之间输入/输出数据的第二仿真器输入/输出电路; 以及数据备份存储电路，用于根据从第二仿真器输入/输出电路输出的监视程序请求信号自动备份存储在与CPU执行的用户程序相对应的CPU的寄存器中的数据，寄存器信号， 寄存器记录信号和寄存器判断信号，并且用于将存储在CPU中的寄存器中的数据应用于与被备份的监视程序改变的用户程序相对应的数据。

公开(公告)号：US5834816A

公开(公告)日：1998-11-10

申请号：US816009

申请日：1997-03-10

申请人： Seong Jin Jang

发明人： Seong Jin Jang

IPC分类号： H01L29/78 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/423 ,  H01L29/76 ,  H01L23/48 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66606 ,  H01L21/28518 ,  H01L21/76889 ,  H01L29/42376 ,  H01L2924/0002 ,  Y10S148/117

摘要： A MOSFET comprising a gate oxide layer on a silicon substrate, a polysilicon gate formed on the gate oxide layer, the length of which gradually widens going from bottom to top, a side gate oxide layer formed by an oxidation process surrounding the polysilicon gate, the side gate oxide layer also gradually widening from bottom to top, a source/drain region beside the gate oxide layer, a connection element having a stacked structure of a polysilicon and/or polycide layer on the field oxide, a doped polysilicon side wall beside the side gate oxide layer and making electric connection between the source/drain region and the connection element.

摘要翻译： 一种MOSFET，包括在硅衬底上的栅极氧化层，形成在栅极氧化物层上的多晶硅栅极，其长度从底部到顶部逐渐变宽，通过围绕多晶硅栅极的氧化工艺形成的侧栅氧化层， 侧栅极氧化物层也从底部向上逐渐变宽，在栅极氧化物层旁边的源极/漏极区域，在场氧化物上具有多晶硅和/或多晶硅化物层的堆叠结构的连接元件，旁边的掺杂多晶硅侧壁 并且在源极/漏极区域和连接元件之间形成电连接。

公开(公告)号：US5703505A

公开(公告)日：1997-12-30

申请号：US369456

申请日：1995-01-06

申请人： Ki Jo Kwon

发明人： Ki Jo Kwon

IPC分类号： H04B15/00 ,  H03K5/08 ,  H03K5/22

CPC分类号： H03K5/082

摘要： A signal reception apparatus has an automatic level selection function. A comparing circuit compares a level of an input signal with a plurality of sensing levels and outputs a plurality of sensing signals in accordance with the compared result. An auto select level controller receives the plurality of sensing signals from the comparing circuit and selects one of the plurality of sensing levels in response to the plurality of sensing signals. The auto select level controller includes a plurality of flip flop stages. Each of the plurality of flip flop stages has a plurality of flip flops connected in series and is coupled to a corresponding one of the plurality of sensing signals from the comparing circuit. A circuit receives the output signals from the plurality of flip flop stages and selects one of the plurality of sensing levels in response to the inputted sensing signals.

摘要翻译： 信号接收装置具有自动电平选择功能。 比较电路将输入信号的电平与多个感测电平进行比较，并根据比较结果输出多个感测信号。 自动选择电平控制器从比较电路接收多个感测信号，并响应于多个感测信号选择多个感测电平中的一个。 自动选择电平控制器包括多个触发器级。 多个触发器级中的每一个具有串联连接的多个触发器，并且被耦合到来自比较电路的多个感测信号中的对应的一个触发器。 电路接收来自多个触发器级的输出信号，并响应于所输入的感测信号选择多个感测电平中的一个。

公开(公告)号：US5681760A

公开(公告)日：1997-10-28

申请号：US367813

申请日：1995-01-03

申请人： Min Hwa Park

发明人： Min Hwa Park

IPC分类号： H01L21/20 ,  H01L21/336 ,  H01L29/786 ,  H01L21/225

CPC分类号： H01L29/78696 ,  H01L21/2022 ,  H01L29/66765 ,  H01L29/78621 ,  H01L29/78678

摘要： A method for manufacturing a thin film transistor is disclosed. To solve the problems of leakage current generated at the grain boundary which passes through a source and a drain and the difficulty in obtaining stable device characteristic owing to the change of the lengths of the channel region and the offset region according to the degree of the overlay misalignment, the method includes the steps of forming a polysilicon layer on a substrate, forming an impurity-containing layer on the polysilicon layer, forming a prescribed pattern by patterning the impurity-containing layer, flowing the impurity-containing layer by heat treating, and crystallizing the polysilicon layer by annealing using a prescribed light source, wherein the flowed impurity-containing layer functions a lens during crystallizing the polysilicon layer to generate a partial temperature difference between the portion of the polysilicon layer where the impurity-containing layer is formed and the portion of the polysilicon layer where the impurity-containing layer is not formed.

摘要翻译： 公开了一种制造薄膜晶体管的方法。 为了解决在通过源极和漏极的晶界处产生的漏电流的问题以及由于沟道区域和偏移区域的长度的变化而导致的难以获得稳定的器件特性， 该方法包括以下步骤：在衬底上形成多晶硅层，在多晶硅层上形成含杂质层，通过图案化杂质含量层，通过热处理使含杂质层流动，形成规定图案;以及 通过使用规定的光源进行退火来使多晶硅层结晶，其中流动的含杂质层在结晶多晶硅层期间起作用，从而在形成含杂质层的多晶硅层的部分和 不形成含杂质层的多晶硅层的部分。

公开(公告)号：US5650957A

公开(公告)日：1997-07-22

申请号：US730256

申请日：1996-10-15

申请人： Jong Moo Choi

发明人： Jong Moo Choi

IPC分类号： H01L27/10 ,  H01L21/8242 ,  H01L27/108 ,  H01L27/12 ,  G11C11/404

CPC分类号： H01L27/1082 ,  H01L27/1203

摘要： A semiconductor memory cell and a process for formation thereof is disclosed. A capacitor is disposed below a transistor, so that a DRAM cell that may be suitable for a high density semiconductor device is produced. A semiconductor device according to the present invention includes: a buried capacitor consisting of a storage electrode, a dielectric layer and a plate electrode formed on a substrate in a planar form; and a transistor formed above the capacitor, a source/drain region of the transistor being connected to the storage electrode of the capacitor.

摘要翻译： 公开了一种半导体存储单元及其形成工艺。 电容器设置在晶体管的下方，从而制造可适用于高密度半导体器件的DRAM单元。 根据本发明的半导体器件包括：由平面形式形成在基板上的存储电极，电介质层和平板电极组成的埋入电容器; 以及形成在电容器上方的晶体管，晶体管的源极/漏极区域连接到电容器的存储电极。

公开(公告)号：US5629540A

公开(公告)日：1997-05-13

申请号：US482534

申请日：1995-06-07

申请人： Jae-sung Roh ,  Hyeung-Tae Kim

发明人： Jae-sung Roh ,  Hyeung-Tae Kim

IPC分类号： H01L21/8242 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/10852 ,  H01L27/10817

摘要： The capacitor area is increased with a cylinder-shaped first storage electrode overlapped with a second electrode in an area which covers two adjacent cells. Included in a semiconductor device using the invention may be: a semiconductor substrate; a word line on the substrate; impurity regions at opposite sides of the word line in the substrate; a first contact hole on an odd impurity region; a first storage electrode connected to the first contact hole, which is overlapped with an adjacent even cell; a first sidewall storage electrode at opposite sides of the first storage electrode; a second contact hole on the even impurity region, the second contact hole having an insulated sidewall; a second storage electrode connected to the second contact hole, which is overlapped with an adjacent odd cell; a second sidewall storage electrode at opposite sides of the second storage electrode.

摘要翻译： 在覆盖两个相邻单元的区域中，与第二电极重叠的圆筒状的第一存储电极增加电容器面积。 包括在使用本发明的半导体器件中可以是：半导体衬底; 衬底上的字线; 在衬底中的字线的相对侧的杂质区域; 奇杂杂区上的第一接触孔; 连接到第一接触孔的第一存储电极，其与相邻的偶数单元重叠; 在所述第一存储电极的相对侧的第一侧壁存储电极; 所述偶杂杂质区上的第二接触孔，所述第二接触孔具有绝缘侧壁; 与第二接触孔连接的与相邻的奇数单元重叠的第二存储电极; 在第二存储电极的相对侧的第二侧壁存储电极。

公开(公告)号：US5623264A

公开(公告)日：1997-04-22

申请号：US336686

申请日：1994-11-04

申请人： Yong-In Park

发明人： Yong-In Park

IPC分类号： H04N9/77 ,  H01L27/02 ,  H03M1/06 ,  H03M1/68 ,  H03M1/74 ,  H04N5/14 ,  H04N9/64 ,  H03M1/66

CPC分类号： H03M1/685 ,  H01L27/0203 ,  H04N9/64 ,  H03M1/747 ,  H04N5/14

摘要： A video digital/analog signal converter having a structure whereby the analog elements of the video D/A converter are separated from the digital elements of the video D/A converter and of arranging current cells of each of channels to one well. The present invention includes a Red-decoder group, a Green-decoder group, and a Blue-decoder group for decoding digital data of R, G, and B color channels, respectively, which are inputted in a state synchronized to R, G, and B clocks for controlling digital data of Red, Green, and Blue color channels. A plurality of data buses transfers digital data of R, G, and B color channel decoded at the R, G, and B decoder groups. First R, G, and B current cell matrixes generate current in response to digital data of the R, G, and B color data inputted from the data buses. Second R, G, and B current cell matrixes generates current in response to digital data of the R, G, and B color channel inputted through the data buses. The bias circuit transfers biases to the first R, G, and B current cell matrixes and the second R, G, and B current matrixes.

摘要翻译： 一种视频数字/模拟信号转换器，其具有将视频D / A转换器的模拟元件与视频D / A转换器的数字元件分离并将每个通道的当前单元排列到一个孔的结构。 本发明包括红色解码器组，绿色解码器组和蓝色解码器组，用于分别以与R，G同步的状态输入的R，G和B色彩通道的数字数据， 和B时钟，用于控制红色，绿色和蓝色通道的数字数据。 多个数据总线传送在R，G和B解码器组解码的R，G和B彩色信道的数字数据。 第一R，G和B当前单元矩阵响应于从数据总线输入的R，G和B颜色数据的数字数据产生电流。 第二R，G和B当前单元矩阵响应于通过数据总线输入的R，G和B彩色通道的数字数据产生电流。 偏置电路将偏置传递到第一个R，G和B当前单元矩阵以及第二个R，G和B电流矩阵。

公开(公告)号：US5605612A

公开(公告)日：1997-02-25

申请号：US337065

申请日：1994-11-10

申请人： Hyeon S. Park ,  Kyu C. Lee ,  Chul H. Kwon ,  Dong H. Yun ,  Hyun W. Shin ,  Hyung K. Hong

发明人： Hyeon S. Park ,  Kyu C. Lee ,  Chul H. Kwon ,  Dong H. Yun ,  Hyun W. Shin ,  Hyung K. Hong

IPC分类号： G01N27/12 ,  G01N33/00 ,  G01N27/26

CPC分类号： G01N27/12 ,  G01N33/0031

摘要： A thin-film gas sensor and manufacturing method of the same is disclosed which includes a silicon substrate; an insulating layer formed on the surface of the silicon substrate; a heater formed in zigzag on the surface of said insulating layer; a temperature sensor formed in zigzag on the surface of the insulating layer in parallel with the heater; an interlayer insulating layer for electrically insulating the heater and temperature sensor formed on the insulating layer; a plurality of electrodes formed on the interlayer insulating layer placed between the heater and temperature sensor; a plurality of pairs of gas sensing layers disposed in an array on the electrodes and for reacting on detected gas; and a plurality of gas shielding layers formed on one gas sensing layer out of the pair of gas sensing layers and for shielding the detected gas so that the gas sensing layers do not react on the detected gas.

摘要翻译： 公开了一种薄膜气体传感器及其制造方法，其包括硅衬底; 形成在所述硅衬底的表面上的绝缘层; 在所述绝缘层的表面上以锯齿形形成的加热器; 绝缘层的表面上与加热器平行地以锯齿形形成的温度传感器; 用于使形成在绝缘层上的加热器和温度传感器电绝缘的层间绝缘层; 多个电极，形成在位于加热器和温度传感器之间的层间绝缘层上; 多个成对的气体感测层，阵列设置在电极上并用于对检测到的气体进行反应; 以及多个气体屏蔽层，形成在一对气体感测层之间的一个气体感测层上，并用于屏蔽检测到的气体，使得气体感测层不对检测到的气体起反应。

公开(公告)号：US5602506A

公开(公告)日：1997-02-11

申请号：US362299

申请日：1994-12-22

申请人： Tae-Hoon Kim ,  Young-Hyun Jun

发明人： Tae-Hoon Kim ,  Young-Hyun Jun

IPC分类号： H01L27/04 ,  G11C5/14 ,  G11C11/408 ,  H01L21/822 ,  H02M3/07 ,  G05F1/10

CPC分类号： G11C5/146 ,  H02M3/07 ,  H01L2924/0002

摘要： A back bias voltage generator comprising a power-on signal generator for generating a power-on signal when an external voltage remains at a constant level, a reference voltage generator for generating a reference voltage in response to the power-on signal from the power-on signal generator, an internal voltage generator for generating an internal voltage and an internal/external voltage select signal in response to the reference voltage from the reference voltage generator, the internal voltage being constant in level, a back bias voltage sensor for generating an oscillation enable signal in response to the external voltage or the internal voltage from the internal voltage generator under control of the internal/external voltage select signal from the internal voltage generator, an oscillator for generating an oscillating signal at a desired period and an enable signal in response to the oscillation enable signal from the back bias voltage sensor and outputting the generated enable signal to the internal voltage generator, and a back bias voltage pump for performing a voltage pumping operation in response to the oscillating signal from the oscillator to generate a desired level of back bias voltage and outputting the generated back bias voltage to an external circuit and the back bias voltage sensor.

摘要翻译： 背偏置电压发生器，其包括用于当外部电压保持在恒定电平时产生通电信号的上电信号发生器，用于响应于来自电源开关信号的电源接通信号产生参考电压的参考电压发生器， 信号发生器，内部电压发生器，用于响应于来自参考电压发生器的参考电压产生内部电压和内部/外部电压选择信号，内部电压水平恒定;用于产生振荡的反向偏置电压传感器 在来自内部电压发生器的内部/外部电压选择信号的控制下，响应于来自内部电压发生器的外部电压或内部电压的使能信号，用于在期望周期产生振荡信号的振荡器和响应中的使能信号 到来自背偏压电压传感器的振荡使能信号，并输出所产生的使能信号 内部电压发生器和反向偏置电压泵，用于响应于来自振荡器的振荡信号进行电压抽运操作，以产生期望电平的反向偏置电压，并将产生的反向偏置电压输出到外部电路，并且 背偏置电压传感器。

公开(公告)号：US5556803A

公开(公告)日：1996-09-17

申请号：US480720

申请日：1995-06-07

申请人： Kyung S. Lee

发明人： Kyung S. Lee

IPC分类号： H01L27/148 ,  H01L29/423 ,  H01L21/70

CPC分类号： H01L27/148 ,  H01L29/42396

摘要： A charged coupled device structure (CCD) and a method for fabricating the CCD structure, which induces a maximum potential distribution difference by utilizing gate insulation films having different physical properties. The charged coupled device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a plurality of first electrodes spaced at fixed intervals over the first insulation layer, a second insulation layer formed only between the plurality of first electrodes and the first insulation layer, a third insulation layer formed over the entire exposed surface of the first electrodes and the first insulation layer, and a plurality of second electrodes formed only on the surface area corresponding to spaces between the plurality of first electrodes. This gate insulation layers having different physical properties induces a maximum potential distribution difference in a semiconductor substrate with a dielectric constant difference between the insulation layers.

摘要翻译： 电荷耦合器件结构（CCD）和用于制造CCD结构的方法，其通过利用具有不同物理性质的栅极绝缘膜来诱导最大电位分布差异。 所述带电耦合器件包括半导体衬底，形成在所述半导体衬底上的第一绝缘层，在所述第一绝缘层上以固定间隔隔开的多个第一电极，仅在所述多个第一电极和所述第一绝缘层之间形成的第二绝缘层 形成在第一电极和第一绝缘层的整个暴露表面上的第三绝缘层，以及仅形成在对应于多个第一电极之间的空间的表面区域上的多个第二电极。 具有不同物理性质的栅极绝缘层在绝缘层之间的介电常数差异引起半导体衬底中的最大电位分布差异。