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公开(公告)号：US11164804B2
公开(公告)日：2021-11-02
申请号：US16519277
申请日：2019-07-23
发明人： Charles L. Arvin , Kevin Drummond , Luca Del Carro , Thomas Brunschwiler , Stephanie Allard , Kenneth C. Marston , Marcus E. Interrante
IPC分类号： H01L23/10 , H01L23/31 , H01L21/56 , H01L23/053 , H01L23/057 , H01L23/367 , H01L25/065 , H01L23/00
摘要： An IC device package includes a carrier, one or more IC devices and a lid. The lid includes a lid-ridge. The lid is connected to the carrier by connecting the lid-ridge to the carrier with first nano particle metallic paste, prior to connecting the IC device to the carrier. Subsequent to connecting the IC device to the carrier, the lid is connected to the lid-ridge with second nano particle metallic paste. The nano particle metallic paste may be sintered to form a metallic connection. In multi-IC device packages, the lid-ridge may be positioned between the lid and the carrier and between the IC devices.
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公开(公告)号：US11158562B2
公开(公告)日：2021-10-26
申请号：US16787241
申请日：2020-02-11
IPC分类号： H01L23/40 , H05K7/20 , F28F13/00 , H01L23/427
摘要： An integrated circuit (IC) device package includes an IC device connected to an upper surface of the IC device carrier. Due to operation conditions or IC device package makeup, the IC device may warp. The warped IC device may include a convex upper surface. A conformable lid is connected to the IC device and includes an internal chamber and a deformable floor. The deformable floor is able to deform or bend along with the IC device. After deformation, the deformable floor may include a concave lower surface. A uniform bond line thickness of a thermal interface material that connects the IC device and the conformable lid is able to be achieved due to the deformable floor deforming or bending along with the IC device.
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公开(公告)号：US11152282B1
公开(公告)日：2021-10-19
申请号：US16906015
申请日：2020-06-19
发明人： Charles Leon Arvin , Kevin Drummond , Kenneth Charles Marston , Chris Muzzy , Sushumna Iruvanti
IPC分类号： H01L23/36 , H01L23/433 , H01L21/48
摘要： An IC device package includes an IC device that is connected to a lid by a thermal interface material (TIM). A catalyst material is formed upon one or more regions upon an upper surface of the IC device and/or an under surface of the lid. The catalyst material increases the rate of crosslinking of polymer chains of the TIM during TIM curing and/or increases the strength of crosslinks that link polymer chains of the TIM during TIM curing. The catalytically enhanced regions have a higher coefficient of heat transfer relative to non-catalytically enhanced regions. Therefore, the catalytically enhanced regions efficiently transfer heat from the IC device to the lid.
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公开(公告)号：US11080222B2
公开(公告)日：2021-08-03
申请号：US15862030
申请日：2018-01-04
摘要： An optical electromagnetic radiation (EM) emitter and receiver are located upon a printed circuit board (PCB) glass security layer. A predetermined reference flux or interference pattern, respectively, is an expected flux or reflection pattern of EM emitted from the EM emitter, transmitted by the glass security layer, and received by the EM receiver. When the PCB is subject to an unauthorized access thereof the optical EM transmitted by glass security layer is altered. An optical monitoring device that monitors the flux or interference pattern of the optical EM received by the EM receiver detects a change in flux or interference pattern, in relation to the reference flux or reference interference pattern, respectively, and passes a tamper signal to one or more computer system devices to respond to the unauthorized access. For example, one or more cryptographic adapter card or computer system functions or secured crypto components may be disabled.
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公开(公告)号：US10948247B2
公开(公告)日：2021-03-16
申请号：US16519632
申请日：2019-07-23
发明人： Paul F. Bodenweber , Kamal K. Sikka
摘要： A heat sink includes a first fin and a second fin. The spacing between the first fin and the second fin may be adjusted by a threaded rod. The threaded rod may include a first portion that is engaged with the first fin and a second portion that is engaged with the second fin. The thread pitch of the first portion and the second portion may differ. For example, the pitch of a first internal thread of the first fin may be smaller than the pitch of a second internal thread of the second fin. The spacing of the heat sink fins may be adjusted based upon the current operating conditions of the electronic device to maintain an optimal temperature of a heat generating device during device operation.
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公开(公告)号：US10901030B2
公开(公告)日：2021-01-26
申请号：US16278905
申请日：2019-02-19
发明人： Max S. Cioban , Jonathan Fry , Michael Rizzolo , Tuhin Sinha
摘要： An integrated circuit (IC) device, such as a wafer, die, or the like, includes a viscoelastic pad upon a contact. The viscoelastic pad includes a viscoelastic material and an electrically conductive material within the viscoelastic material. The viscoelastic pad provides for a probe needle of an IC device tester to be electrically connected to the IC device contact without the probe needle directly contacting the IC device contact. The viscoelastic pad may be probed multiple instances by the probe needle and may be washed or otherwise removed from the IC device after testing is completed. The viscoelastic pad may be formed upon the IC device by forming the viscoelastic material within a mask, aligning the viscoelastic pad to the IC device contact, and ejecting the viscoelastic material from the mask upon the IC device contact.
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公开(公告)号：US10651083B2
公开(公告)日：2020-05-12
申请号：US15911313
申请日：2018-03-05
发明人： Andrew Tae Kim , Baozhen Li , Ernest Y. Wu , Chih-Chao Yang
IPC分类号： H01L23/52 , H01L21/768 , H01L23/532
摘要： A graded cap is formed upon an interconnect, such as a back end of line wire. The graded cap includes a microstructure that uniformly changes from a metal nearest the interconnect to a metal nitride most distal from the interconnect. The graded cap is formed by nitriding a metal cap that is formed upon the interconnect. During nitriding an exposed one or more perimeter portions of the metal cap become a metal nitride with a larger amount or concentration of Nitrogen while one or more inner portions of the metal cap nearest the interconnect may be maintained as the metal or become the metal nitride with a fewer amount or concentration of Nitrogen. The resulting graded cap includes a gradually or uniformly changing microstructure between the one or more inner portions and the one or more perimeter portions.
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公开(公告)号：US10607928B1
公开(公告)日：2020-03-31
申请号：US16529002
申请日：2019-08-01
发明人： Anson J. Call , Sushumna Iruvanti , Shidong Li , Brian W. Quinlan , Kamal K. Sikka , Rui Wang
IPC分类号： H01L23/498 , H01L23/00 , H01L21/48 , H01L23/31 , H01L23/367 , H01L23/433 , H01L23/053 , H01L23/10
摘要： An integrated circuit (IC) device carrier, such as a chip carrier, die carrier, or the like, includes a contact that locally reduces laminate strain within the IC device carrier. One type of contact pad described includes tapered sidewall(s). For example, a positively tapered contact pad includes one or more sidewalls obtusely angled relative to the contact surface of the IC carrier and a negatively tapered contact pad includes one or more sidewalls acutely angled relative to the contact surface of the IC carrier. Another type of contact pad described includes a contact pad connected to one or more pillars. The pillar(s) are also connected to a ring formed within an internal wiring level of the IC device carrier.
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公开(公告)号：US10580772B2
公开(公告)日：2020-03-03
申请号：US16051820
申请日：2018-08-01
IPC分类号： H01L27/088 , H01L21/8234 , H01L29/16 , H01L29/51 , H01L29/165 , H01L21/762 , H01L29/06 , H01L21/02 , H01L21/82 , H01L21/8238 , H01L21/3105
摘要： A semiconductor structure includes fins that have a 2D material, such as Graphene, upon at least the fin sidewalls. The thickness of the 2D material sidewall may be tuned to achieve desired finFET band gap control. Neighboring fins of the semiconductor structure form fin wells. The semiconductor structure may include a fin cap upon each fin and the 2D material is formed upon the sidewalls of the fin and the bottom surface of the fin wells. The semiconductor structure may include a well-plug at the bottom of the fin wells and the 2D material is formed upon the sidewalls and upper surface of the fins. The semiconductor structure may include both fin caps and well-plugs such that the 2D material is formed upon the sidewalls of the fins.
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公开(公告)号：US10566313B1
公开(公告)日：2020-02-18
申请号：US16106577
申请日：2018-08-21
发明人： Shidong Li , Kamal K. Sikka
IPC分类号： H01L25/065 , H01L23/367 , H01L21/56 , H01L23/00 , H01L23/373 , H01L23/34 , H01L23/42 , H01L23/552 , H01L23/36
摘要： An integrated circuit (IC) chip carrier includes an IC chip electrically connected to an IC chip carrier by a plurality of chip-carrier contacts, a cover thermally connected the IC chip upper surface, and an in-plane thermal conductance (ITC) layer upon the IC chip carrier between the IC chip carrier and the IC chip. The ITC layer includes an extension tab connected to a vertical side surface of the cover. Heat is transferred vertically from the IC chip to the cover. Heat is also transferred vertically from the IC chip to the ITC layer. Heat is also transferred within the ITC layer through the ITC layer basal plane(s). The ITC layer basal plane(s) are positioned horizontally where the ITC layer is between the IC chip and the IC chip carrier. The ITC layer basal planes are positioned vertically where the extension tab contacts the vertical side surface of the cover.
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