公开(公告)号：US06597621B2

公开(公告)日：2003-07-22

申请号：US09791778

申请日：2001-02-26

申请人： Takaharu Tsuji ,  Akinori Shibayama

发明人： Takaharu Tsuji ,  Akinori Shibayama

IPC分类号： G11C700

CPC分类号： G11C8/12 ,  G11C11/4085 ,  G11C11/4087

摘要： In a semiconductor memory device with a plurality of banks having a plurality of memory sub array, according to a mode setting signal, data access control is made depending on whether access is made on a memory sub array basis or a bank basis. A multi-bank semiconductor memory device is provided capable of easily implementing both of a low power consumption mode and a long page size mode.

公开(公告)号：US6160753A

公开(公告)日：2000-12-12

申请号：US504781

申请日：2000-02-15

申请人： Akinori Shibayama

发明人： Akinori Shibayama

IPC分类号： G11C11/41 ,  G11C8/14 ,  G11C11/401 ,  G11C11/407 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/108 ,  G11C8/08

CPC分类号： G11C8/14

摘要： Each sub-word line drive circuit SWD in a sub-word line drive section SWLB receives a signal carried by a main word line MWL0, a sub-word line non-selection signal XWD, and a sub-word line drive signal WD to drive a sub-word line SW. The sub-word line non-selection signal XWD is generated by an inverter XWDG in an intersection region SDR based on the sub-word line drive signal WD received by the inverter. The active level of the sub-word line drive signal WD is an internal boosted potential VPP which is higher than the external supply potential VDD. By using as the inactive level of the sub-word line non-selection signal XWD an internal lowered potential VINT which is lower than the external supply potential VDD, power consumption of an internal boosted potential generation circuit is reduced.

摘要翻译： 子字线驱动部分SWLB中的每个子字线驱动电路SWD接收由主字线MWL0，子字线非选择信号XWD和子字线驱动信号WD所携带的信号以驱动 子字线SW。 子字线非选择信号XWD由交流区域SDR中的反相器XWDG基于由逆变器接收的子字线驱动信号WD产生。 子字线驱动信号WD的有效电平是比外部电源电位VDD高的内部升压电位VPP。 通过将子字线非选择信号XWD的无效电平用作低于外部电源VDD的内部降低电位VINT，内部升压电位产生电路的功耗降低。

公开(公告)号：US5545977A

公开(公告)日：1996-08-13

申请号：US74561

申请日：1993-06-09

申请人： Toshio Yamada ,  Akinori Shibayama ,  Shunichi Iwanari ,  Atsushi Fujiwara

发明人： Toshio Yamada ,  Akinori Shibayama ,  Shunichi Iwanari ,  Atsushi Fujiwara

IPC分类号： G05F1/24 ,  G05F1/613 ,  G05F3/24 ,  G11C11/407 ,  G11C11/408 ,  H01L27/10 ,  H03K19/00 ,  G05F3/22

CPC分类号： G05F3/245 ,  Y10S323/907

摘要： In a circuit, a resistance element is interposed between a positive power supply line (external power supply voltage level VCC) and an output node. To feedback an output potential, there is disposed an N-type MOSFET of which gate is connected to the output node and of which source is connected to the earth line (earth potential VSS) in the circuit. Another three N-type MOSFETs which are so connected in series to one another as to form a MOS diode, are interposed between the drain of the feedback N-type MOSFET and the output node. The earth line also serves as a reference potential line for the potential of the output node. Variations of the threshold voltages of the MOSFETs due to temperature variations are compensated. This restrains the output potential from varying.

摘要翻译： 在电路中，在正电源线（外部电源电压电平VCC）和输出节点之间插入电阻元件。 为了反馈输出电位，设置了一个N型MOSFET，其栅极连接到输出节点，并且其中的源极连接到电路中的地线（地电位VSS）。 在反馈N型MOSFET的漏极和输出节点之间插入另外三个彼此串联连接形成MOS二极管的N型MOSFET。 地线也可作为输出节点电位的参考电位线。 由于温度变化导致的MOSFET的阈值电压的变化被补偿。 这就抑制了输出电位的变化。

公开(公告)号：US4293819A

公开(公告)日：1981-10-06

申请号：US76428

申请日：1979-09-17

申请人： Akinori Shibayama ,  Kenji Maio ,  Norio Yokozawa

发明人： Akinori Shibayama ,  Kenji Maio ,  Norio Yokozawa

IPC分类号： H03F3/34 ,  H03F1/30 ,  H03F3/45 ,  H03F1/02

CPC分类号： H03F3/45479 ,  H03F1/30

摘要： A high-speed low-drift operational amplifier is disclosed in which a coefficient circuit having a voltage gain of more than 1 is formed employing a low frequency operational amplifier with a low-drift characteristic to multiply an input voltage by the voltage gain, the coefficient circuit and a low pass filter are connected in cascade to form a drift compensating circuit, and the inverting and non-inverting input terminals of a wide-band operational amplifier are connected to the input and output terminals of the drift compensating circuit, respectively.

摘要翻译： 公开了一种高速低漂移运算放大器，其中使用具有低漂移特性的低频运算放大器形成具有大于1的电压增益的系数电路，以将输入电压乘以电压增益，系数 电路和低通滤波器级联连接形成漂移补偿电路，宽带运算放大器的反相和非反相输入端分别连接到漂移补偿电路的输入和输出端。

公开(公告)号：US07290234B2

公开(公告)日：2007-10-30

申请号：US11122221

申请日：2005-05-05

申请人： Akinori Shibayama

发明人： Akinori Shibayama

IPC分类号： G06F17/50

CPC分类号： G06F17/5068 ,  H01L27/0207

摘要： In transistor layout design, a plurality of distances Lfig1, Lfig2, Lfig3 from a gate electrode of a transistor to the edge of a diffusion layer are displayed by multiple lines according to a variation amount of a transistor characteristic with the use of a CAD tool. A layer for defining an isolation region between adjacent transistors is extended automatically by the CAD tool. Accordingly, even in the case where the transistor characteristic varies depending on the distance from the gate electrode of the transistor to the edge of the diffusion layer, the isolation region between the adjacent transistors can be layouted and designed optimally with no measurement of the distance by designer's visual observation necessitated.

摘要翻译： 在晶体管布局设计中，从晶体管的栅电极到扩散层的边缘的多个距离Lfig 1，Lfig 2，Lfig 3根据晶体管特性的变化量通过多行显示，使用 CAD工具。 用于定义相邻晶体管之间的隔离区域的层由CAD工具自动扩展。 因此，即使在晶体管特性根据从晶体管的栅电极到扩散层的边缘的距离而变化的情况下，相邻晶体管之间的隔离区域可以被布置和设计为最佳而不测量距离 设计师的视觉观察需要。

公开(公告)号：US06920079B2

公开(公告)日：2005-07-19

申请号：US10902133

申请日：2004-07-30

申请人： Akinori Shibayama

发明人： Akinori Shibayama

IPC分类号： G11C11/41 ,  G11C11/412 ,  H01L21/8244 ,  H01L27/11 ,  G11C7/00

CPC分类号： G11C11/412 ,  H01L27/11

摘要： A semiconductor memory device according to the present invention includes: a plurality of N-ch MOS transistors arranged in an area surrounding a plurality of memory cells arranged in an array, at a spacing depending on a spacing of the plurality of memory cells, for driving the plurality of memory cells; and a plurality of dummy transistors 32-j each of which is formed between two adjacent ones of the plurality of N-ch MOS transistors 30-k so as to share diffusion layers with adjacent N-ch MOS transistors 30 and each of which has a gate electrode supplied with a voltage for electrically insulating these adjacent transistors 30-k.

摘要翻译： 根据本发明的半导体存储器件包括：多个N沟道MOS晶体管，其布置在以阵列布置的多个存储单元的区域中，其间隔取决于多个存储单元的间隔，用于驱动 所述多个存储单元; 以及多个虚设晶体管32-j，每个虚拟晶体管32-j分别形成在多个N沟道MOS晶体管30-k中的两个相邻的N沟道MOS晶体管30-k之间，以便与相邻的N沟道MOS晶体管30共享扩散层， 栅电极被提供有用于使这些相邻晶体管30-k电绝缘的电压。

公开(公告)号：US5881012A

公开(公告)日：1999-03-09

申请号：US633684

申请日：1996-04-17

申请人： Toshiaki Kawasaki ,  Akinori Shibayama

发明人： Toshiaki Kawasaki ,  Akinori Shibayama

IPC分类号： G11C11/413 ,  G11C5/14 ,  G11C11/407 ,  H03K17/06 ,  H03K3/353

CPC分类号： G11C5/145 ,  H03K17/063

摘要： A frequency switching circuit is controlled by a low address strobe signal XRAS. A sub-boosted power supply generating circuit is driven at a low frequency generated by a first oscillating circuit during the standby of a DRAM, and at a high frequency generated by a second oscillating circuit during the operation of the DRAM. The sub-boosted power supply generating circuit is driven in a shorter cycle during the operation than during the standby. Consequently, charges are supplied to a booster power source to boost the voltage level thereof. Accordingly, even if the period of the operation state is increased, a drop in voltage level of the boosted power supply caused by a transistor off leak current and a junction leak current can be controlled. Thus, the malfunction of a circuit can be prevented from occurring due to the drop in voltage level of the boosted power supply. The drop in voltage level of the boosted power supply can be controlled during the operation of the DRAM so that it is possible to implement a boosted power supply generating circuit which can prevent the malfunction of the circuit from occurring.

摘要翻译： 频率切换电路由低地址选通信号XRAS控制。 次级升压电源发生电路在DRAM的待机期间由第一振荡电路产生的低频驱动，并且在DRAM的操作期间由第二振荡电路产生的高频驱动。 次升压电源发生电路在操作期间以比待机期间更短的周期被驱动。 因此，电荷被提供给升压电源以升高其电压电平。 因此，即使操作状态的周期增加，可以控制由晶体管断开漏电流和结漏电流引起的升压电源的电压电平的下降。 因此，可以防止由于升压电源的电压电平的下降而发生电路的故障。 可以在DRAM的操作期间控制升压电源的电压电平的下降，使得可以实现可以防止电路故障发生的升压电源产生电路。

公开(公告)号：US5554953A

公开(公告)日：1996-09-10

申请号：US132322

申请日：1993-10-06

申请人： Akinori Shibayama ,  Toshio Yamada

发明人： Akinori Shibayama ,  Toshio Yamada

IPC分类号： G11C11/407 ,  G05F1/46 ,  G05F1/56 ,  G05F3/26 ,  G11C11/403 ,  H01L27/10 ,  G05F3/02

CPC分类号： G05F1/465

摘要： A reference voltage generator is composed of a first constant-voltage generator consisting of three p-type MOS transistors for generating a first reference voltage Vref for use in the normal operation, which is independent of an external power-supply voltage VCC and of a second constant-voltage generator consisting of two p-type MOS transistors and one n-type MOS transistor for generating a second reference voltage Vrefbi for use in a burn-in acceleration test, which is dependent on VCC. The output of each of the constant-voltage generators is feedbacked to the other constant-voltage generator as its input. Two differential amplifiers and two output drivers output, as an internal reduced voltage Vint, the higher one of Vref and Vrefbi which are outputted from the reference voltage generator. Since Vint is generated based on the two outputs Vref and Vrefbi which are outputted from the single reference voltage generator and which are related to each other, the power consumption and layout area of an internal reduced-voltage generator, which is suitable for the burn-in, can be reduced.

公开(公告)号：US5341035A

公开(公告)日：1994-08-23

申请号：US709961

申请日：1991-06-04

申请人： Akinori Shibayama ,  Toshio Yamada

发明人： Akinori Shibayama ,  Toshio Yamada

IPC分类号： G05F3/20 ,  H03L1/00 ,  H03L5/00

CPC分类号： G05F3/205

摘要： In a substrate potential generator, a substrate potential is supplied by a substrate potential supplier controlled by a substrate potential detector. The substrate potential detector sends a setting signal having a hysteresis characteristic relative to the substrate potential. That is, the setting signal is higher when the substrate potential supplier is stopped than when the substrate potential supplier is activated or when negative charges are injected into the substrate potential. Thus, the operation of the substrate potential supplier is stopped after the substrate potential becomes lower than the lower setting potential when the substrate potential supplier is activated, while the operation of the substrate potential supplier is started after the substrate potential becomes higher than the upper setting potential after the operation of the substrate potential supplier is stopped. Therefore, the starting and stopping of the substrate potential supplier is not repeated so frequently, so that the dissipating charge and discharge currents accompanied with the starting and stopping will not be enhanced wastefully.

摘要翻译： 在衬底电位发生器中，由衬底电位检测器控制的衬底电位供给器提供衬底电位。 衬底电位检测器发送具有相对于衬底电位的滞后特性的设置信号。 也就是说，当衬底电位供给器停止时，设置信号比衬底电位供应器被激活时或当负电荷注入衬底电位时更高。 因此，在基板电位供给器被激活之后，在基板电位变得低于基板电位供给器的下限设定电位之后，基板电位供给器的动作停止，同时基板电位供给器的动作在基板电位变得高于上限值之后开始 在停止基板电位供给器的操作之后的潜力。 因此，不会如此频繁地重复基板电位供给器的启动和停止，从而不会浪费地增加伴随启动和停止的耗散充放电电流。

公开(公告)号：US4994753A

公开(公告)日：1991-02-19

申请号：US169598

申请日：1988-03-17

申请人： Takashi Ikeguchi ,  Manabu Matsumoto ,  Shinjiroo Ueda ,  Tadasi Sonobe ,  Toru Murashita ,  Satoshi Ido ,  Kazuo Kuroishi ,  Akinori Shibayama

发明人： Takashi Ikeguchi ,  Manabu Matsumoto ,  Shinjiroo Ueda ,  Tadasi Sonobe ,  Toru Murashita ,  Satoshi Ido ,  Kazuo Kuroishi ,  Akinori Shibayama

IPC分类号： H05H7/00

CPC分类号： H05H7/00

摘要： An industrial compact synchrotron radiation source includes, for the purpose of prolonging lifetime of a charged particle beam, beam absorbers made of a material having a low photodesorption yield and disposed inside a bending section/vacuum chamber at at least positions upon which the synchrotron radiation is irradiated, and electrically conductive beam stabilizers disposed at positions inside the bending section/vacuum chamber which are distant by a predetermined distance from an orbit of the charged particle beam toward the outer circumferential wall of the bending section/vacuum chamber.