公开(公告)号：US20110254118A1

公开(公告)日：2011-10-20

申请号：US12763287

申请日：2010-04-20

申请人： Zia Alan Shafi ,  Jeffrey A. Babcock

发明人： Zia Alan Shafi ,  Jeffrey A. Babcock

IPC分类号： H01L29/872 ,  H01L21/22 ,  H01L21/329

CPC分类号： H01L29/7835 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/872

摘要： A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

摘要翻译： 肖特基二极管通过在位于肖特基二极管的金属 - 硅结和肖特基二极管的n +阴极接触之间的区域上形成绝缘控制栅极来优化肖特基二极管的导通状态电阻，反向漏电流和反向击穿电压 肖特基二极管。

公开(公告)号：US20110140204A1

公开(公告)日：2011-06-16

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US20090127659A1

公开(公告)日：2009-05-21

申请号：US11985429

申请日：2007-11-15

申请人： Zia Alan Shafi

发明人： Zia Alan Shafi

IPC分类号： H01L29/73 ,  H01L21/04

CPC分类号： H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/1004 ,  H01L29/66272 ,  H01L29/7322

摘要： The collector resistance of a bipolar junction transistor that is formed in a CMOS process is substantially reduced by forming a heavily-doped collector extension region that extends from a heavily-doped collector contact region down to a deep well of the same conductivity type to a point that lies close to the base of the transistor.

摘要翻译： 在CMOS工艺中形成的双极结型晶体管的集电极电阻通过形成从重掺杂的集电极接触区域向下延伸到相同导电类型的深阱的重掺杂集电极延伸区域而大大减小， 靠近晶体管的基极。

公开(公告)号：US08815667B2

公开(公告)日：2014-08-26

申请号：US12639158

申请日：2009-12-16

申请人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

发明人： Michael Smith ,  Vladimir Mikhalev ,  Puneet Sharma ,  Zia Alan Shafi ,  Henry Jim Fulford

IPC分类号： H01L21/338

CPC分类号： H01L29/7833 ,  H01L21/266 ,  H01L27/105 ,  H01L29/0634 ,  H01L29/0692 ,  H01L29/0847 ,  H01L29/423 ,  H01L29/6659

摘要： Methods of forming transistors and transistors are disclosed, such as a transistor having a gate dielectric over a semiconductor having a first conductivity type, a control gate over the gate dielectric, source and drain regions having a second conductivity type in the semiconductor having the first conductivity type, and strips having the second conductivity type within the semiconductor having the first conductivity type and interposed between the control gate and at least one of the source and drain regions.

摘要翻译： 公开了形成晶体管和晶体管的方法，例如在具有第一导电类型的半导体上具有栅极电介质的晶体管，栅极电介质上的控制栅极，具有第一导电性的半导体中的第二导电类型的源极和漏极区域 型和具有第二导电类型的带在具有第一导电类型的半导体内并且插入在控制栅极和源极和漏极区域中的至少一个之间的条带。

公开(公告)号：US20090127629A1

公开(公告)日：2009-05-21

申请号：US11985428

申请日：2007-11-15

申请人： Zia Alan Shafi

发明人： Zia Alan Shafi

IPC分类号： H01L21/8248 ,  H01L27/10

CPC分类号： H01L27/0623 ,  H01L21/8228 ,  H01L21/8249 ,  H01L27/082

摘要： NPN and PNP bipolar junction transistors are formed in a semiconductor substrate material in a double polysilicon CMOS process flow in a manner that allows the collectors of both of the npn and pnp bipolar transistors to be biased differently than the bias that is placed on the semiconductor substrate material.

摘要翻译： NPN和PNP双极结型晶体管以双重多晶硅CMOS工艺流程形成在半导体衬底材料中，以允许npn和pnp双极晶体管两者的集电极与放置在半导体衬底上的偏置不同地偏置 材料。

公开(公告)号：US20120244689A1

公开(公告)日：2012-09-27

申请号：US13486166

申请日：2012-06-01

申请人： Zia Alan Shafi ,  Jeffrey A. Babcock

发明人： Zia Alan Shafi ,  Jeffrey A. Babcock

IPC分类号： H01L21/04

CPC分类号： H01L29/7835 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/872

摘要： A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

摘要翻译： 肖特基二极管通过在位于肖特基二极管的金属 - 硅结和肖特基二极管的n +阴极接触之间的区域上形成绝缘控制栅极来优化肖特基二极管的导通状态电阻，反向漏电流和反向击穿电压 肖特基二极管。

公开(公告)号：US08193602B2

公开(公告)日：2012-06-05

申请号：US12763287

申请日：2010-04-20

申请人： Zia Alan Shafi ,  Jeffrey A. Babcock

发明人： Zia Alan Shafi ,  Jeffrey A. Babcock

IPC分类号： H01L29/66

CPC分类号： H01L29/7835 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/872

摘要： A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

摘要翻译： 肖特基二极管通过在位于肖特基二极管的金属 - 硅结和肖特基二极管的n +阴极接触之间的区域上形成绝缘控制栅极来优化肖特基二极管的导通状态电阻，反向漏电流和反向击穿电压 肖特基二极管。

公开(公告)号：US06372652B1

公开(公告)日：2002-04-16

申请号：US09494633

申请日：2000-01-31

申请人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

发明人： Purakh Raj Verma ,  Zia Alan Shafi ,  Yu Shan ,  Zeng Zheng ,  Manju Sarkar ,  Shao-Fu Sanford Chu

IPC分类号： H01L21302

CPC分类号： H01L23/5256 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method for forming a thin film, electrically blowable fuse with reproducible blowing wattage using a sacrificial metal patch over a fuse dielectric layer and two etch processes; wherein the first etch process is selective to the metal patch and the second etch process is selective to the fuse dielectric layer. A fuse element, having an element width, is formed over a semiconductor structure, and a fuse dielectric layer is formed over the fuse element. A sacrificial metal patch is formed on the fuse dielectric layer; wherein the patch width being greater than the fuse element width. A second dielectric layer is formed on the sacrificial metal patch, and additional metal layers and dielectric layers may be formed over the second dielectric layer, but only the dielectric layers will remain over the fuse element. The second dielectric layer and any overlying dielectric layers are patterned to form a fuse window opening, having a width greater than the sacrificial metal patch, using a first fuse window etch selective to the sacrificial metal patch. Then, the sacrificial metal patch is etched through the fuse window opening using a second fuse window etch selective to the fuse dielectric layer, leaving a reproducible thickness of the fuse dielectric layer overlying the fuse element; thereby providing a reproducible blowing wattage.

摘要翻译： 一种用于在熔丝电介质层和两个蚀刻工艺上使用牺牲金属贴片形成具有可再现的吹扫功率的薄膜电可熔电熔丝的方法; 其中所述第一蚀刻工艺对所述金属贴片是选择性的，并且所述第二蚀刻工艺对所述熔丝电介质层是选择性的。 在半导体结构上形成具有元件宽度的熔丝元件，并且在保险丝元件上形成熔丝电介质层。 在熔丝绝缘层上形成牺牲金属贴片; 其中所述贴片宽度大于所述熔丝元件宽度。 在牺牲金属贴片上形成第二电介质层，并且可以在第二电介质层上形成附加的金属层和电介质层，但是只有电介质层将保留在熔丝元件上方。 使用对牺牲金属贴片选择性的第一熔丝窗口蚀刻，将第二电介质层和任何上覆电介质层图案化以形成具有大于牺牲金属贴片的宽度的熔丝窗口。 然后，使用对熔丝电介质层选择性的第二熔丝窗蚀刻，通过熔丝窗口蚀刻牺牲金属贴片，留下覆于熔丝元件上的熔丝电介质层的可再现厚度; 从而提供可重复的吹制瓦数。

公开(公告)号：US08728920B2

公开(公告)日：2014-05-20

申请号：US13486166

申请日：2012-06-01

申请人： Zia Alan Shafi ,  Jeffrey A. Babcock

发明人： Zia Alan Shafi ,  Jeffrey A. Babcock

IPC分类号： H01L21/425

CPC分类号： H01L29/7835 ,  H01L27/0629 ,  H01L29/0649 ,  H01L29/0692 ,  H01L29/872

摘要： A Schottky diode optimizes the on state resistance, the reverse leakage current, and the reverse breakdown voltage of the Schottky diode by forming an insulated control gate over a region that lies between the metal-silicon junction of the Schottky diode and the n+ cathode contact of the Schottky diode.

摘要翻译： 肖特基二极管通过在位于肖特基二极管的金属 - 硅结和肖特基二极管的n +阴极接触之间的区域上形成绝缘控制栅极来优化肖特基二极管的导通状态电阻，反向漏电流和反向击穿电压 肖特基二极管。

公开(公告)号：US08207559B2

公开(公告)日：2012-06-26

申请号：US12498141

申请日：2009-07-06

申请人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

发明人： Jeffrey A. Babcock ,  Natalia Lavrovskaya ,  Saurabh Desai ,  Alexei Sadovnikov ,  Zia Alan Shafi

IPC分类号： H01L29/66

CPC分类号： H01L27/095 ,  H01L27/0207 ,  H01L29/1029 ,  H01L29/1058 ,  H01L29/808 ,  H01L29/812

摘要： In accordance with an aspect of the invention, A Schottky junction field effect transistor (JFET) is created using cobalt silicide, or other Schottky material, to form the gate contact of the JFET. The structural concepts can also be applied to a standard JFET that uses N− type or P− type dopants to form the gate of the JFET. In addition, the structures allow for an improved JFET linkup with buried linkup contacts allowing improved noise and reliability performance for both conventional diffusion (N− and P− channel) JFET structures and for Schottky JFET structures. In accordance with another aspect of the invention, the gate poly, as found in a standard CMOS or BiCMOS process flow, is used to perform the linkup between the source and the junction gate and/or between the drain and the junction gate of a junction filed effect transistor (JFET). Use of a bias on the gate linkup of the JFET allows an additional tuning knob for the JFET that can be optimized to trade off breakdown characteristics with reduced on resistance. In accordance with yet another aspect of the invention, a patterned buried layer is used to form the back gate control for a junction field effect transistor (JFET). The structure allows a layout or buried layer pattern change to adjust the pinch-off voltage of the JFET structure. Vertical and lateral diffusion of the buried layer is used to adjust the JFET operating parameters with a simple change in the buried layer patterns. In addition, the structures allow for increased breakdown voltage by leveraging charge sharing concepts and improving channel confinement for power JFET structures. These concepts can also be applied to both N− channel and P− channel diffusion JFETs and to Schottky JFET structures.

摘要翻译： 根据本发明的一个方面，使用硅化钴或其它肖特基材料制造肖特基结场效应晶体管（JFET），以形成JFET的栅极接触。 结构概念也可以应用于使用N型或P-型掺杂剂形成JFET栅极的标准JFET。 此外，这些结构允许改进的JFET与嵌入式连接触点连接，从而可以改善常规扩散（N和P沟道）JFET结构和肖特基JFET结构的噪声和可靠性性能。 根据本发明的另一方面，如标准CMOS或BiCMOS工艺流程中所发现的栅极聚合体用于执行源极和结栅极之间和/或在结的漏极和结栅之间的连接 场效应晶体管（JFET）。 在JFET的栅极连接上使用偏置可以为JFET提供一个额外的调谐旋钮，该调谐旋钮可以优化，以降低导通电阻的击穿特性。 根据本发明的另一方面，图案化掩埋层用于形成结型场效应晶体管（JFET）的背栅极控制。 该结构允许布局或掩埋层图案改变以调节JFET结构的夹断电压。 掩埋层的垂直和横向扩散用于通过掩埋层图案的简单变化来调节JFET操作参数。 此外，这些结构允许通过利用电荷共享概念并改善功率JFET结构的通道限制来增加击穿电压。 这些概念也可以应用于N沟道和P沟道扩散JFET以及肖特基JFET结构。