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    Manufacturing of a semiconductor device and corresponding semiconductor device
    1.
    发明授权
    Manufacturing of a semiconductor device and corresponding semiconductor device 有权
    制造半导体器件和相应的半导体器件

    公开(公告)号：US08841186B2

    公开(公告)日：2014-09-23

    申请号：US13582142

    申请日：2010-03-04

    Applicant: Alexander Hoelke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Yang Hao

    Inventor： Alexander Hoelke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Yang Hao

    IPC: H01L21/336 ,  H01L29/78 ,  H01L29/06 ,  H01L29/10 ,  H01L21/265 ,  H01L29/66 ,  H01L29/423

    CPC classification number: H01L21/26586 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).

    Abstract translation: 所公开的制造（110,120,130,140）半导体器件（12）的方法具有以下步骤：形成半导体器件的主体（44）的至少一个壁（33） （12）通过将用于半导体器件（12）的栅极（42）的至少一个沟槽（22）蚀刻到主体（44）中; 以及在所述至少一个沟槽（22）的所述蚀刻（112）之后并且在涂覆所述至少一个沟槽（22）之前，在所述主体（44）的所述至少一个壁（33）中执行倾斜注入掺杂（126,128） 具有绝缘层（29）的沟槽（22）。 半导体器件（12）包括用于半导体器件（12）的栅极（42）的至少一个沟槽（22）; 以及具有所述至少一个沟槽（22）的至少一个壁（33）的主体（44），其中沿着深度方向（do）的距离（66）的掺杂浓度（62）的偏差（64） 在所述至少一个壁（33）的表面（33）中的所述至少一个沟槽（22）的距离小于所述距离（66）的所述掺杂浓度（62）的最大值（68）的百分之十。

    Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation electronics, and production method
    2.
    发明授权
    Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation electronics, and production method 失效
    光检测器包括单片集成跨阻放大器和评估电子器件，以及生产方法

    公开(公告)号：US07491925B2

    公开(公告)日：2009-02-17

    申请号：US10596035

    申请日：2004-12-06

    Applicant: Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

    Inventor： Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

    IPC: H03F3/08

    CPC classification number: H01L27/144 ,  H01L31/02016 ,  H01L31/022408 ,  H01L31/10

    Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evaluation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

    Abstract translation: 本发明的目的是配置光电检测器（10），使得在现有技术中已知的检测器上特别是当对评估电子器件进行单片整合时，不会产生用于处理低发光强度的缺点。 所述目的通过用于处理低发光强度的光电检测器实现，其包括单片集成跨阻抗放大器和单片集成评估电子器件。 实际的光电池组件（20）被分配给光优选落在其上的芯片面。 电子电路部件（30）布置在相对的芯片面上。 在光电管和电子电路之间的电连接（40）在垂直于芯片法线的方向上具有延伸。

    Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation electronics, and production method
    4.
    发明申请
    Photodetector comprising a monolithically integrated transimpedance amplifier and evaluation electronics, and production method 失效
    光检测器包括单片集成跨阻放大器和评估电子器件，以及生产方法

    公开(公告)号：US20070164393A1

    公开(公告)日：2007-07-19

    申请号：US10596035

    申请日：2004-12-06

    Applicant: Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

    Inventor： Konrad Bach ,  Alexander Hoelke ,  Uwe Eckoldt ,  Wolfgang Einbrodt ,  Karl-Ulrich Stahl

    IPC: H01L29/00

    CPC classification number: H01L27/144 ,  H01L31/02016 ,  H01L31/022408 ,  H01L31/10

    Abstract: The aim of the invention is to configure a photodetector (10) such that no disadvantages are created for processing low luminous intensities on detectors known in prior art, especially when monolithically integrating the evalation electronics. Said aim is achieved by a photodetector for processing low luminous intensities, comprising a monolithically integrated transimpedance amplifier and monolithically integrated evaluation electronics. An actual photocell component (20) is assigned to the chip face onto which the light preferably falls. Electronic circuit components (30) are arranged on the opposite chip face. Electrical connections (40) between the photocell and the electronic circuit are provided with an extension in the direction running perpendicular to the chip normal.

    Abstract translation: 本发明的目的是配置光电检测器（10），使得在现有技术中已知的检测器上特别是当对评估电子器件进行单片整合时，不会产生用于处理低发光强度的缺点。 所述目的通过用于处理低发光强度的光电检测器实现，其包括单片集成跨阻抗放大器和单片集成评估电子器件。 实际的光电池组件（20）被分配给光优选落在其上的芯片面。 电子电路部件（30）布置在相对的芯片面上。 在光电管和电子电路之间的电连接（40）在垂直于芯片法线的方向上具有延伸。

    MANUFACTURING OF A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE
    6.
    发明申请
    MANUFACTURING OF A SEMICONDUCTOR DEVICE AND CORRESPONDING SEMICONDUCTOR DEVICE 有权
    半导体器件的制造和相应的半导体器件

    公开(公告)号：US20120319193A1

    公开(公告)日：2012-12-20

    申请号：US13582142

    申请日：2010-03-04

    Applicant: Alexander Hoelke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Yang Hao

    Inventor： Alexander Hoelke ,  Deb Kumar Pal ,  Kia Yaw Kee ,  Yang Hao

    IPC: H01L21/336 ,  H01L29/78

    CPC classification number: H01L21/26586 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/1033 ,  H01L29/4236 ,  H01L29/66659 ,  H01L29/7835 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The disclosed method of manufacturing (110, 120, 130, 140) a semiconductor device (12) has the steps (112, 114, 116) of: forming at least one wall (33) of a body (44) of the semiconductor device (12) by etching at least one trench (22) for a gate (42) of the semiconductor device (12) into the body (44); and performing a slanted implantation doping (126, 128) into the at least one wall (33) of the body (44), after the etching (112) of the at least one trench (22) and prior to coating the at least one trench (22) with an insulating layer (29). A semiconductor device (12) comprises at least one trench (22) for a gate (42) of the semiconductor device (12); and a body (44) having at least one wall (33) of the at least one trench (22), wherein a deviation (64) of a doping concentration (62) along a distance (66) in depth-direction (do) of the at least one trench (22) in a surface (33) of the at least one wall (33) is less than ten percent of a maximum value (68) of the doping concentration (62) along the distance (66).

    Abstract translation: 所公开的制造（110,120,130,140）半导体器件（12）的方法具有以下步骤：形成半导体器件的主体（44）的至少一个壁（33） （12）通过将用于半导体器件（12）的栅极（42）的至少一个沟槽（22）蚀刻到主体（44）中; 以及在所述至少一个沟槽（22）的所述蚀刻（112）之后并且在涂覆所述至少一个沟槽（22）之前，在所述主体（44）的所述至少一个壁（33）中执行倾斜注入掺杂（126,128） 具有绝缘层（29）的沟槽（22）。 半导体器件（12）包括用于半导体器件（12）的栅极（42）的至少一个沟槽（22）; 以及具有所述至少一个沟槽（22）的至少一个壁（33）的主体（44），其中沿着深度方向（do）的距离（66）的掺杂浓度（62）的偏差（64） 在所述至少一个壁（33）的表面（33）中的所述至少一个沟槽（22）的距离小于所述距离（66）的所述掺杂浓度（62）的最大值（68）的百分之十。

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