公开(公告)号：US5886376A

公开(公告)日：1999-03-23

申请号：US673974

申请日：1996-07-01

申请人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

发明人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7881

摘要： An electrically erasable programmable read-only memory CEEPROM) includes a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

摘要翻译： 电可擦除可编程只读存储器CEEPROM）包括场效应晶体管和在第一绝缘层上间隔开的控制栅极，形成在场效应晶体管上的第二绝缘层和控制栅极以及第二绝缘层上的公共浮栅 层叠在场效应晶体管和控制栅极的沟道上，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。 本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

公开(公告)号：US5567635A

公开(公告)日：1996-10-22

申请号：US245724

申请日：1994-05-17

申请人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Being S. Wu

发明人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Being S. Wu

IPC分类号： H01L21/8247 ,  G11C16/12 ,  G11C16/14 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/10844 ,  G11C16/12 ,  G11C16/14 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

摘要： The objects of the present invention are accomplished by merging a MOS-FET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate.

摘要翻译： 本发明的目的是通过将MOS-FET器件和浮栅合并成三维沟槽结构来实现的。 沟槽器件单元具有四个垂直边和底部。 沟槽的底部形成EEPROM单元的转移FET的沟道区。 重掺杂源极和漏极区域形成在沟槽的两个垂直侧壁上并相对地面对。 重掺杂区域覆盖整个侧壁并且具有大于沟槽深度的深度，使得沟道区域由沟槽的底部限定。 沟槽的剩余的两个垂直侧壁由隔离氧化物形成。 第一二氧化硅层覆盖沟槽的底部并形成电池器件的栅极氧化物的一部分。 第二个二氧化硅层覆盖沟槽的垂直侧壁。 第二二氧化硅层相对于栅极氧化物层相对较薄。 第二二氧化硅层将源极和漏极区域与覆盖第一和第二二氧化硅层的浮置栅极分开。 浮置栅极与所有四个沟槽侧壁重叠，并且基本上增加了浮动栅极和控制栅极之间的耦合。

公开(公告)号：US5331188A

公开(公告)日：1994-07-19

申请号：US841343

申请日：1992-02-25

申请人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

发明人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

IPC分类号： H01L27/105 ,  G11B17/028 ,  G11C14/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L29/68 ,  G11C11/24

CPC分类号： B82Y10/00 ,  G11C14/00

摘要： The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.

摘要翻译： 本发明涉及一种具有双层浮置栅极的单晶体管非易失性DRAM单元，以在电源中断期间允许存储电容器的内容被传送到浮动栅极。 浮动栅极的第一层通过隧道氧化物与存储电容器的存储节点分离，以允许浮置栅极和存储电容器之间的电子隧穿。 在本发明的另一个实施例中，双电子注入器结构设置在单层浮动和存储节点之间，以允许电子注入浮动栅极和存储节点之间。 在本发明的另一个实施例中，实现擦除栅极以去除浮动栅极上的电荷。 擦除栅极可以通过隧道氧化物或单个电子注入器结构与浮动栅极分离，以允许电子从浮动栅极行进到擦除栅极。

公开(公告)号：US5389567A

公开(公告)日：1995-02-14

申请号：US241136

申请日：1994-05-10

申请人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

发明人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

IPC分类号： H01L27/105 ,  G11B17/028 ,  G11C14/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

CPC分类号： B82Y10/00 ,  G11C14/00

摘要： The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.

摘要翻译： 本发明涉及一种具有双层浮置栅极的单晶体管非易失性DRAM单元，以在电源中断期间允许存储电容器的内容被传送到浮动栅极。 浮动栅极的第一层通过隧道氧化物与存储电容器的存储节点分离，以允许浮置栅极和存储电容器之间的电子隧穿。 在本发明的另一个实施例中，双电子注入器结构设置在单层浮动和存储节点之间，以允许电子注入浮动栅极和存储节点之间。 在本发明的另一个实施例中，实现擦除栅极以去除浮动栅极上的电荷。 擦除栅极可以通过隧道氧化物或单个电子注入器结构与浮动栅极分离，以允许电子从浮动栅极行进到擦除栅极。

公开(公告)号：US5315142A

公开(公告)日：1994-05-24

申请号：US855956

申请日：1992-03-23

申请人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Being S. Wu

发明人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Being S. Wu

IPC分类号： H01L21/8247 ,  G11C16/12 ,  G11C16/14 ,  H01L21/336 ,  H01L21/8242 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/78

CPC分类号： H01L27/10844 ,  G11C16/12 ,  G11C16/14 ,  H01L27/115 ,  H01L29/66825 ,  H01L29/7883

摘要： The objects of the present invention are accomplished by merging a MOSFET device and a floating gate into a three dimensional trench structure. The trench device cell has four vertical sides and bottom. The bottom of the trench forms the channel region of the transfer FET of the EEPROM cell. The heavily doped source and drain regions are formed on two vertical sidewalls of the trench and oppositely face each other. The heavily doped regions cover the entire sidewall and have a depth which is greater than the trench depth so that the channel region is defined by the bottom of the trench. The remaining two vertical sidewalls of the trench are formed by isolation oxide. A first silicon dioxide layer covers the bottom of the trench and forms part of the gate oxide of the cell device. A second silicon dioxide layer covers the vertical sidewalls of the trench. The second silicon dioxide layer is relatively thin with respect to the gate oxide layer. The second silicon dioxide layer separates the source and drain regions from the floating gate which overlays both the first and second silicon dioxide layers. The floating gate overlaps all four trench sidewalls and substantially increases the coupling between the floating-gate and the control-gate. A control gate overlies the floating gate and the control gate is separated from the floating gate by a separate dielectric layer. The second silicon dioxide layer is relatively thin so that tunneling of electrons between the vertical sidewalls which incorporate the source and drain regions and the floating gate will occur. Tunnelling is the mechanism which charges and discharges the floating gate. The trench EEPROM memory structure of the present invention occupies a small amount of surface area while maintaining a high coupling ratio between the control gate and the floating gate. The high coupling ratio between the floating-gate and the control-gate is maintained because the floating gate is butted to isolation oxide on two sides of the trench. The trench EEPROM memory structure of the present invention also reduces program and erase time because the floating gate can be programmed or charged through either the source or drain regions in many cells at one time.

公开(公告)号：US5960265A

公开(公告)日：1999-09-28

申请号：US881628

申请日：1997-06-24

申请人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

发明人： Alexandre Acovic ,  Tak Hung Ning ,  Paul Michael Solomon

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/423 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/115 ,  H01L27/1203 ,  H01L29/42324 ,  H01L29/7881

摘要： An EEPROM device is described incorporating a field effect transistor and a control gate spaced apart on a first insulating layer, a second insulating layer formed over the field effect transistor and the control gate and a common floating gate on the second insulating layer over the channel of the field effect transistor and the control gate, the floating gate thus also forms the gate electrode of the field-effect transistor. The EEPROM devices may be interconnected in a memory array and a plurality of memory arrays may be stacked on upon another. The invention overcomes the problem of using a non-standard silicon-on-insulator (SOI) CMOS process to make EEPROM arrays with high areal density.

摘要翻译： 描述了一种EEPROM器件，其结合了场效应晶体管和在第一绝缘层上间隔开的控制栅极，在场效应晶体管上形成的第二绝缘层和控制栅极以及在第二绝缘层上的公共浮置栅极 场效应晶体管和控制栅极，因此浮置栅极也形成场效应晶体管的栅电极。 EEPROM器件可以互连在存储器阵列中，并且多个存储器阵列可以堆叠在另一个上。 本发明克服了使用非标准绝缘体上硅（SOI）CMOS工艺来制造具有高面密度的EEPROM阵列的问题。

公开(公告)号：US5446299A

公开(公告)日：1995-08-29

申请号：US235768

申请日：1994-04-29

申请人： Alexandre Acovic ,  Ben S. Wu

发明人： Alexandre Acovic ,  Ben S. Wu

IPC分类号： H01L21/8247 ,  H01L21/84 ,  H01L27/105 ,  H01L27/115 ,  H01L27/12 ,  H01L29/786 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L27/11521 ,  H01L21/84 ,  H01L27/115 ,  H01L27/1203 ,  H01L29/7883

摘要： A stacked gate memory cell for a memory cell array is disclosed that is constructed on a SOI substrate and contains a second control gate buried underneath the conducting channel of the cell in addition to a first wordline control gate that is disposed over a floating gate changing the voltage on the second control gate will modulate the potential of the floating channel, which allows a specific cell of the array to be selected and the programmed or erased by FN tunneling through the floating gate and channel without disturbing adjacent cells. While reading the information stored in the floating gate, the second control gate can also be used to prevent disturb. The second control gate is in parallel with the bit line and perpendicular with the first word line control gate. The floating gate and the cell is located at the cross point of the first and second control gates. Therefore, by varying the voltage on the first and second control gates only, the cell can be programmed or erased through FN tunneling.

摘要翻译： 公开了一种用于存储单元阵列的堆叠栅极存储单元，其被构造在SOI衬底上，并且除了设置在浮置栅极上的第一字线控制栅极之外还包含埋在电池的导电沟道下方的第二控制栅极， 第二控制栅极上的电压将调制浮动通道的电位，这允许选择阵列的特定单元，并通过FN穿通浮动栅极和通道进行编程或擦除，而不会干扰相邻单元。 在读取存储在浮动栅极中的信息时，第二控制栅极也可用于防止干扰。 第二控制栅极与位线并联并与第一字线控制栅极垂直。 浮动栅极和单元位于第一和第二控制栅极的交叉点处。 因此，通过仅改变第一和第二控制栅极上的电压，可以通过FN隧道对单元进行编程或擦除。

公开(公告)号：US5411905A

公开(公告)日：1995-05-02

申请号：US236752

申请日：1994-04-29

申请人： Alexandre Acovic ,  Ben S. Wu

发明人： Alexandre Acovic ,  Ben S. Wu

IPC分类号： H01L21/28 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

CPC分类号： H01L29/66825 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/1203 ,  H01L29/7881 ,  H01L29/7883

摘要： A structure and fabrication method for an EEPROM cell having dual channel regions and the floating and control gate folded inside a trench. The cell is built on a SOI film substrate and the bottom part of the floating gate is butted to oxide, which provides high coupling factor. Inside the trench, the floating gates are butted to the conducting channels on two sidewalls, respectively. On the other two sidewalls, the floating gate are butted to the source and drain elements (bit line). These two sidewalls are used as the injection regions of FN tunnelling between source/drain and the floating gate or the isolation regions between bit lines. Since FN tunnelling (program and erase) occurs at the two trench sidewalls against the source and drain, program/erase speed is increased by increasing trench depth while maintaining cell size constant.

摘要翻译： 一种具有双通道区域的EEPROM单元的结构和制造方法，以及在沟槽内折叠的浮动和控制栅极。 电池构建在SOI膜基片上，浮栅的底部对接到氧化物上，提供高耦合系数。 在沟槽内，浮动栅极分别对接在两个侧壁上的导电通道上。 在另外两个侧壁上，浮动栅极对接到源极和漏极元件（位线）。 这两个侧壁用作源极/漏极和浮动栅极之间的FN隧道的注入区域或位线之间的隔离区域。 由于FN沟道（编程和擦除）发生在两个沟槽侧壁相对于源极和漏极，因此通过增加沟道深度同时保持单元尺寸不变，来增加编程/擦除速度。