公开(公告)号：US4435786A

公开(公告)日：1984-03-06

申请号：US324344

申请日：1981-11-23

申请人： Andrew C. Tickle

发明人： Andrew C. Tickle

IPC分类号： G11C14/00 ,  H01L27/11 ,  G11C11/40

CPC分类号： G11C14/00 ,  H01L27/1104 ,  H01L27/1112

摘要： A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

摘要翻译： 具有两个交叉耦合晶体管的自刷新非易失性存储单元包括形成在所述第一晶体管的栅极和沟道之间的第一浮置栅极，所述第一浮置栅极通过隧道氧化物覆盖所述第一晶体管的漏极的一部分， 第二晶体管和形成在所述第二晶体管的栅极和沟道之间的第二浮置栅极，所述第二浮置栅极的一部分覆盖着隧道氧化第一晶体管的漏极的一部分。 设备的电源电压和栅极电压的干扰通常增强而不是降低存储在电池中的数据的状态，从而为电池提供非常长的存储时间。 电池能够在挥发性和非挥发性状态下同时操作。

公开(公告)号：US4398338A

公开(公告)日：1983-08-16

申请号：US219784

申请日：1980-12-24

申请人： Andrew C. Tickle ,  Madhukar B. Vora

发明人： Andrew C. Tickle ,  Madhukar B. Vora

IPC分类号： H01L27/112 ,  G11C16/04 ,  G11C17/00 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/20 ,  H01L21/225

CPC分类号： H01L27/11517 ,  G11C16/0433 ,  H01L27/115

摘要： A process for fabricating an electrically erasable nonvolatile memory cell comprises forming a first region of insulating material which is less than about 200 Angstroms thick on a selected surface portion of an electrically-isolated relatively lightly doped pocket of epitaxial silicon of a first conductivity type such that first and second surface areas of the epitaxial pocket are exposed. Regions of the epitaxial pocket underlying the first and second exposed surface areas are doped such that first and second relatively lightly doped regions of a second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon regions of the first conductivity type are formed on the first insulating region and on the second relatively lightly doped epitaxial region. Insulating material is formed over exposed surfaces of the first polysilicon region and the second polysilicon region such that first and second surface portions of the second relatively lightly doped epitaxial region are exposed. The regions of the epitaxial pocket underlying the surface of the first relatively lightly doped epitaxial region and the first and second surface portions of the second relatively lightly doped epitaxial region are doped such that first, second and third relatively heavily doped epitaxial regions of the second conductivity type are formed in the epitaxial pocket. Relatively heavily doped polysilicon of the second conductivity type is formed on the insulating regions covering said first conductivity type polycrystalline regions.

摘要翻译： 一种用于制造电可擦除非易失性存储单元的工艺包括在第一导电类型的外部硅的电隔离相对轻掺杂的袋的选定表面部分上形成小于约200埃厚的绝缘材料的第一区域，使得 露出外延袋的第一和第二表面区域。 在第一和第二暴露表面区域下面的外延袋的区域被掺杂，使得第二导电类型的第一和第二相对轻掺杂的区域形成在外延袋中。 在第一绝缘区域和第二相对轻掺杂的外延区域上形成第一导电类型的相对重掺杂的多晶硅区域。 绝缘材料形成在第一多晶硅区域和第二多晶硅区域的暴露表面上，使得暴露第二相对轻掺杂的外延区域的第一和第二表面部分。 在第一相对轻掺杂的外延区域的表面下面的外延阱的区域和第二相对轻掺杂的外延区域的第一和第二表面部分被掺杂，使得具有第二导电性的第一，第二和第三相对重掺杂的外延区域 类型形成在外延袋中。 在覆盖所述第一导电型多晶区域的绝缘区域上形成第二导电类型的相对重掺杂的多晶硅。

公开(公告)号：US06351841B1

公开(公告)日：2002-02-26

申请号：US09531725

申请日：2000-03-21

申请人： Andrew C. Tickle

发明人： Andrew C. Tickle

IPC分类号： H01L2350

CPC分类号： G06F17/5068

摘要： A method of creating multi-gate transistors with integrated circuit polygon compactors is disclosed. Specifically, in order to provide a more efficient layout when the size of a transistor is increased during design migration, a small multi-gate transistor is formed by inserting at least one parallel transistor over the diffusion layer of the target transistor, between a gate and contact. The compactor then enforces the new design rules, and adjusts the relative sizes of the parallel transistors as required. The resulting multi-gate transistor structure is much more compact than a single large transistor, providing a more efficient design layout.

摘要翻译： 公开了一种用集成电路多边形压实机制造多栅极晶体管的方法。 具体地说，为了在设计迁移期间晶体管的尺寸增加时提供更有效的布局，通过在目标晶体管的扩散层之间插入至少一个并联晶体管，形成栅极和 联系。 然后，压实机执行新的设计规则，并根据需要调整并联晶体管的相对尺寸。 所得到的多栅极晶体管结构比单个大晶体管更紧凑，提供了更有效的设计布局。

公开(公告)号：US4377857A

公开(公告)日：1983-03-22

申请号：US207859

申请日：1980-11-18

申请人： Andrew C. Tickle

发明人： Andrew C. Tickle

IPC分类号： G11C17/00 ,  G11C8/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/16 ,  G11C16/34 ,  H01L27/10 ,  G11C11/40

CPC分类号： G11C16/3486 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/16 ,  G11C16/3459 ,  G11C16/3468 ,  G11C8/12 ,  G11C2216/28

摘要： An electrically erasable programmable read-only memory (E.sup.2 PROM) is provided which utilizes an inhibit voltage applied to unselected word lines during writing to prevent writing in unselected rows. In the preferred embodiment, each memory cell of the E.sup.2 PROM array consists of a single floating gate field effect transistor. The E.sup.2 PROM of the present invention provides for row erasure and single bit writing.

摘要翻译： 提供了一种电可擦除可编程只读存储器（E2PROM），其在写入期间利用施加到未选择字线的禁止电压以防止在未选择的行中写入。 在优选实施例中，E2PROM阵列的每个存储单元由单个浮栅场效应晶体管组成。 本发明的E2PROM提供行擦除和单位写入。

公开(公告)号：US4435790A

公开(公告)日：1984-03-06

申请号：US474929

申请日：1983-03-14

申请人： Andrew C. Tickle ,  Madhukar B. Vora

发明人： Andrew C. Tickle ,  Madhukar B. Vora

IPC分类号： H01L21/82 ,  H01L27/115 ,  G11C11/40

CPC分类号： H01L21/82 ,  H01L27/115

摘要： A method for encoding binary data into an electrically erasable memory. The memory includes a matrix of memory cells formed as a plurality of rows (X write lines/X sense lines/source lines) and columns (Y sense lines) with each cell including a floating gate field effect PMOS transistor and an NPN bipolar transistor. The method includes applying an erase voltage, e.g. +20 volts, to each of the Y sense lines while maintaining each of the X sense lines at this erase voltage and each of the X write lines at ground and applying the erase voltage to each of the source lines such that each of the PMOS transistors assumes a relatively negative threshold state. The method includes applying a write voltage e.g., +20 volts, to selected X write lines while maintaining unselected X write and selected Y sense lines at ground and unselected Y sense lines at an inhibit voltage e.g., +10 volts, which is less than the write voltage, and maintaining each of the X sense lines at an intermediate voltage e.g., +5 volts, such that the PMOS transistors of memory cells located at the intersections of the selected X write lines and the selected Y sense lines assume a relatively positive threshold state.

摘要翻译： 一种将二进制数据编码为电可擦除存储器的方法。 存储器包括形成为多行（X写入线/ X感测线/源极线）和列（Y感测线）的存储器单元的矩阵，每个单元包括浮置栅极场效应PMOS晶体管和NPN双极晶体管。 该方法包括施加擦除电压，例如， + 20伏，同时将每个X感测线保持在该擦除电压，并将每个X写入线保持在地，并将擦除电压施加到每个源极线，使得每个PMOS晶体管 假定相对负阈值状态。 该方法包括对所选择的X写入线施加例如+ 20伏的写入电压，同时保持未选择的X写入和选择的Y感测线在接地和未选择的Y感测线路处于例如+ 10伏特的抑制电压，其小于 写入电压，并且将每个X检测线保持在例如+ 5V的中间电压，使得位于所选择的X写入线和所选择的Y条线的交点处的存储器单元的PMOS晶体管呈现相对正的阈值 州。

公开(公告)号：US4420497A

公开(公告)日：1983-12-13

申请号：US295417

申请日：1981-08-24

申请人： Andrew C. Tickle

发明人： Andrew C. Tickle

IPC分类号： H01L21/3105 ,  H01L21/314 ,  H01L21/316 ,  H01L21/318 ,  H01L21/326 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  B05D5/12 ,  H01L21/00

CPC分类号： H01L21/02238 ,  H01L21/02255 ,  H01L21/3105 ,  H01L21/3144 ,  H01L21/31662 ,  H01L21/3185 ,  H01L21/326

摘要： Defects in dielectric layers exhibiting low dielectric strength on silicon substrates (11) are deliberately damaged during manufacture to allow their repair by the formation of dielectric plugs (13B). The defects are damaged by the application of an electric field, and are repaired by the selective oxidation or nitridation of the silicon substrate underlying the damaged areas of dielectrics.

摘要翻译： 在硅衬底（11）上表现出低介电强度的电介质层中的缺陷在制造过程中故意损坏，以允许通过形成电介质塞（13B）进行修复。 缺陷被施加电场而损坏，并且通过在损坏的电介质区域下方的硅衬底的选择性氧化或氮化来修复缺陷。

公开(公告)号：US4423491A

公开(公告)日：1983-12-27

申请号：US324343

申请日：1981-11-23

申请人： Andrew C. Tickle

发明人： Andrew C. Tickle

IPC分类号： G11C14/00 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/11 ,  H01L29/788 ,  H01L29/792 ,  G11C11/40

CPC分类号： G11C14/00 ,  H01L27/1104 ,  H01L27/1112

摘要： A self-refreshing non-volatile memory cell having two cross-coupled transistors includes a first floating gate formed between the gate and the channel of said first transistor, said first floating gate overlying by means of a tunnel oxide a portion of the drain of said second transistor and a second floating gate formed between the gate and channel of said second transistor, a portion of said second floating gate overlying by tunnel oxide a portion of the drain of the first transistor. Disturbances in the supply voltage and the gate voltage of the device normally enhance rather than degrade the state of data stored in the cell, thereby providing an extremely long storage time for the cell. The cell is capable of operating simultaneously in a volatile and a non-volatile state.

摘要翻译： 具有两个交叉耦合晶体管的自刷新非易失性存储单元包括形成在所述第一晶体管的栅极和沟道之间的第一浮置栅极，所述第一浮置栅极通过隧道氧化物覆盖所述第一晶体管的漏极的一部分， 第二晶体管和形成在所述第二晶体管的栅极和沟道之间的第二浮置栅极，所述第二浮置栅极的一部分覆盖着隧道氧化第一晶体管的漏极的一部分。 设备的电源电压和栅极电压的干扰通常增强而不是降低存储在电池中的数据的状态，从而为电池提供非常长的存储时间。 电池能够在挥发性和非挥发性状态下同时操作。