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公开(公告)号：US4733077A
公开(公告)日：1988-03-22
申请号：US683983
申请日：1984-12-20
CPC分类号： H04N5/2173
摘要： A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26 which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.
摘要翻译： 公开了一种新技术和使用该技术的输出编码电路，用于在半导体IR检测器23和相关联的输出电路24,25,26之间进行接口，该技术和电路将电荷分组转移到先前存储复位电平的感测电容器22上 信号。 作为输出信号，采用在该电容器22上存在的电压中产生的阶梯式信号变化或Δt。
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2.发明授权
公开(公告)号：US4684800A
公开(公告)日：1987-08-04
申请号：US839398
申请日：1986-03-14
申请人： Arthur L. Morse , Niels A. Thompson
发明人： Arthur L. Morse , Niels A. Thompson
IPC分类号： H01L27/148 , H01L29/768 , H04N5/33 , H04N5/357 , H04N5/372 , H01J40/14 , H01L29/78
CPC分类号： H01L29/76808 , H01L27/14881 , H04N3/1518 , H04N5/33
摘要： A method and circuit for reading out the detector signal current from an infrared focal plane array by converting the detector current into a precisely proportional charge packet which is injected into the channel of a charge-coupled device (CCD). In a preferred embodiment the circuit comprises a capacitive feedback transimpedance amplifier 30 (or similar infrared detector signal encoding circuit) coupled to a precision CCD charge-injection circuit 10 formed on a semiconducting substrate 12. A surface potential well 50 underneath a reservoir gate electrode 80 is filled with charge that is initially kept in place by a channel stop 14 and a potential barrier 62. When the detector signal is applied to signal gate electrode 60, the potential barrier 62 is lowered and a precisely proportional amount of charge fills a store potential well 48 underneath a store gate electorde 85. At an appropriate time the charge in the storage potential well 48 is transferred to CCD channel 90 by means of a clock pulse applied to a transfer gate electorde 100.
摘要翻译： 通过将检测器电流转换成注入到电荷耦合器件（CCD）的沟道中的精确比例的电荷分组来读出来自红外焦平面阵列的检测器信号电流的方法和电路。 在优选实施例中，电路包括耦合到形成在半导体基板12上的精密CCD电荷注入电路10的电容反馈跨阻抗放大器30（或类似的红外检测器信号编码电路）。在储存器栅电极80下方的表面势阱50 充满了最初通过通道阻挡器14和势垒62保持在适当位置的电荷。当检测器信号被施加到信号栅电极60时，势垒62被降低并且精确比例的电荷填充存储电位 在一个适当的时间，存储电位井48中的电荷通过施加到转移门极100的时钟脉冲被转移到CCD通道90。
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3.发明授权Charge integrating-type analog to digital converter employing rapid charge neutralization and N-bit feedback 失效电荷积分型模数转换器采用快速电荷中和和N位反馈
公开(公告)号：US5652586A
公开(公告)日：1997-07-29
申请号：US406238
申请日：1995-03-17
申请人： Thomas Y. Chuh , Arthur L. Morse
发明人： Thomas Y. Chuh , Arthur L. Morse
CPC分类号： H03M1/60
摘要： A Sigma Rho A/D converter (10) includes a transconductance element (R) having an input node for receiving an input voltage signal V.sub.in and an output node providing an analog current I.sub.in ; a charge integrator (12) having an input coupled to the output node, the charge integrator having feedback provided by an integrating capacitor C and an output node providing an output signal V.sub.o ; and a clocked voltage comparator (14) having an input coupled to V.sub.o for comparing V.sub.o to a reference potential. An output of the comparator updates in response to an occurrence of a first clock signal CLK1. A current sink (16) is switchably coupled to the output node of the transconductance element as a function of the logic state of the output of the comparator. A sum and dump accumulator (18) has an input coupled to the output of the comparator and an output having N output bits, and operates to sum together individual ones of first logic states and outputs a sum value on the N output bits in response to an occurrence of a second clock signal CLK2. The frequency of CLK2 is equal to CLK1/N. A unique bit stream is output from the comparator (14) for each allowed input voltage such that complete information about the input voltage is embedded within, or encoded by, the bit stream output from the comparator.
摘要翻译： Sigma Rho A / D转换器（10）包括跨导元件（R），其具有用于接收输入电压信号Vin的输入节点和提供模拟电流Iin的输出节点; 具有耦合到输出节点的输入的电荷积分器（12），所述电荷积分器具有由积分电容器C提供的反馈和提供输出信号Vo的输出节点; 和时钟电压比较器（14），其具有耦合到Vo的输入，用于将Vo与参考电位进行比较。 比较器的输出响应于第一时钟信号CLK1的发生而更新。 作为比较器的输出的逻辑状态的函数，电流吸收器（16）可切换地耦合到跨导元件的输出节点。 和和转储累加器（18）具有耦合到比较器的输出的输入端和具有N个输出位的输出，并且操作以将各个第一逻辑状态相加在一起，并响应于 发生第二时钟信号CLK2。 CLK2的频率等于CLK1 / N。 对于每个允许的输入电压，从比较器（14）输出唯一的比特流，使得关于输入电压的完整信息嵌入在由比较器输出的比特流内或由比较器输出的比特流中编码。
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公开(公告)号：US4843395A
公开(公告)日：1989-06-27
申请号：US95500
申请日：1987-09-11
申请人： Arthur L. Morse
发明人： Arthur L. Morse
IPC分类号： H03M1/00
CPC分类号： H03M1/10
摘要： An analog-to-digital converter system for converting an input analog signal having a wide dynamic range to a digital output has a non-linear function generator for compressing the wide dynamic range input signal to a reduced dynamic range signal, an analog-to-digital converter of limited dynamic range for converting the reduced dynamic range signal to a digitally formatted signal, and a conversion memory for providing a digital value corresponding to the value of the wide range analog input. The digitally formatted signal addresses a word within the conversion memory, the word so addressed containing a digital value corresponding to the magnitude of the analog input signal. Each word of the conversion memory has a sufficient number of bits for expressing the desired dynamic range of the input signal. In one embodiment of the invention a digital counter and a digital to analog converter provides for calibrating the system, the output of the counter being stored in the conversion memory which, in this embodiment, is composed of RAM data storage elements.
摘要翻译： 用于将具有宽动态范围的输入模拟信号转换为数字输出的模数转换器系统具有用于将宽动态范围输入信号压缩到减小的动态范围信号的非线性函数发生器， 用于将减小的动态范围信号转换为数字格式化信号的有限动态范围的数字转换器，以及用于提供对应于宽范围模拟输入的值的数字值的转换存储器。 数字格式化的信号寻址转换存储器内的一个字，这样写入的字包含对应于模拟输入信号幅度的数字值。 转换存储器的每个字都具有用于表示输入信号的期望动态范围的足够数量的位。 在本发明的一个实施例中，数字计数器和数模转换器提供校准系统，存储在转换存储器中的计数器的输出在本实施例中由RAM数据存储元件组成。
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公开(公告)号：US4743762A
公开(公告)日：1988-05-10
申请号：US895649
申请日：1986-08-12
CPC分类号： H04N5/2173
摘要： A new technique, and output encoding circuits using that technique, are disclosed for interfacing between a semiconductor IR detector 23 and associated output electronics 24, 25, 26, which technique and circuits transfer a charge packet onto a sense capacitor 22 that previously stored a reset level signal. The resulting stepped signal change, or delta, in the voltage present on that capacitor 22 is employed as the output signal.
摘要翻译： 公开了一种新技术和使用该技术的输出编码电路，用于在半导体IR检测器23和相关联的输出电路24,25,26之间进行接口，该技术和电路将电荷分组转移到先前存储复位的感测电容器22上 电平信号。 作为输出信号，采用在该电容器22上存在的电压中产生的阶梯式信号变化或Δt。
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公开(公告)号：US4523326A
公开(公告)日：1985-06-11
申请号：US458607
申请日：1983-01-17
申请人： Mary J. Hewitt , Arthur L. Morse
发明人： Mary J. Hewitt , Arthur L. Morse
CPC分类号： H04N3/1568 , H01L27/14831
摘要： Noise reduction and dynamic range expansion in a CCD imager is achieved by combining a narrow FAT zero metering gate with a reference column subtraction and CCD charge bailing.
摘要翻译： CCD成像器中的降噪和动态范围扩展通过将窄的FAT零计量门与参考列减法和CCD电荷保存组合来实现。
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公开(公告)号：US4978872A
公开(公告)日：1990-12-18
申请号：US437787
申请日：1989-11-20
IPC分类号： G01J5/22 , G06G7/186 , H01L27/148
CPC分类号： H01L27/14881 , G01J5/22 , G06G7/1865
摘要： An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.
摘要翻译： 一种用于大规模集成结构形成的检测器阵列中的红外检测器10的放大器电路12。 放大器电路与结构上的检测器一起制造，并且包括与检测器10电容耦合14的放大器级和输出级。 提供开关FET 16以选择性地将检测器耦合到外部偏置源，并且提供另一个开关FET 24以在积分周期之后复位放大器级。 在一个实施例中，输出级28包括通过开关FET 32选择性地耦合到放大器级的存储电容器30.在另一实施例中，输出编码级28包括用于控制存储电容器30上的电压的双栅极FET 32。 双栅极FET控制周期性地对电容器进行脉冲和漏极的电压源。 一个FET门连接到放大器级输出，另一个连接到时钟信号。 在另一个实施例中，输出级128包括具有较小电容的第二电容器132，第一电容器130与放大器级的输出成比例的电荷放在其上用于随后的采样。
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公开(公告)号：US4786831A
公开(公告)日：1988-11-22
申请号：US682112
申请日：1984-12-17
CPC分类号： H01L27/14881 , G01J5/22 , G06G7/1865
摘要： An amplifier circuit 12 for an infrared detector 10 in a detector array formed on a large-scale integrated structure. The amplifier circuit is fabricated along with the detector on the structure and includes an amplifier stage capacitively coupled 14 to the detector 10 and an output stage. A switching FET 16 is provided to selectively couple the detector to an external biasing source and another switching FET 24 is provided to reset the amplifier stage after an integration period. In one embodiment the output stage 28 includes a storage capacitor 30 selectively coupled to the amplifier stage by a switching FET 32. In another embodiment the output encoding stage 28 includes a two-gate FET 32 to control the voltage on a storage capacitor 30. The two-gate FET controls a voltage source which periodically pulses and drains the capacitor. One FET gate is connected to the amplifier stage output and the other is connected to a clocking signal. In still another embodiment the output stage 128 includes a second capacitor 132 of smaller capacitance onto which a charge of the first capacitor 130 proportional to the output of the amplifier stage is placed for subsequent sampling.
摘要翻译： 一种用于大规模集成结构形成的检测器阵列中的红外检测器10的放大器电路12。 放大器电路与结构上的检测器一起制造，并且包括与检测器10电容耦合14的放大器级和输出级。 提供开关FET 16以选择性地将检测器耦合到外部偏置源，并且提供另一个开关FET 24以在积分周期之后复位放大器级。 在一个实施例中，输出级28包括通过开关FET 32选择性地耦合到放大器级的存储电容器30.在另一实施例中，输出编码级28包括用于控制存储电容器30上的电压的双栅极FET 32。 双栅极FET控制周期性地对电容器进行脉冲和漏极的电压源。 一个FET门连接到放大器级输出，另一个连接到时钟信号。 在另一个实施例中，输出级128包括具有较小电容的第二电容器132，第一电容器130与放大器级的输出成比例的电荷放在其上用于随后的采样。
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