公开(公告)号：US08161657B2

公开(公告)日：2012-04-24

申请号：US12909293

申请日：2010-10-21

申请人： Takeshi Yamamoto ,  Atsushi Shimaoka

发明人： Takeshi Yamamoto ,  Atsushi Shimaoka

IPC分类号： G01B7/28

CPC分类号： G01B5/201 ,  G01B3/008 ,  G01B5/016

摘要： A position controller provided in a controlling module obtains a difference between a detected rotation angle of a stylus and a target rotation angle, and determines an energization amount to a voice coil motor so that the difference becomes zero. A variable limiter circuit limits a driving current, which is supplied from the position controller, to a limitation value so that a rotation force applied to the stylus from the voice coil motor is constant. A target rotation angle issuing portion switches over the target rotation angle based on a relative position of a contact portion of the stylus.

摘要翻译： 设置在控制模块中的位置控制器获得检测到的触针的旋转角度和目标旋转角度之间的差异，并且确定对音圈电动机的通电量，使得差值变为零。 可变限幅器电路限制从位置控制器提供的驱动电流到限制值，使得从音圈电机施加到触控笔的旋转力是恒定的。 目标旋转角度发出部分基于触针的接触部分的相对位置切换目标旋转角度。

公开(公告)号：US20050169038A1

公开(公告)日：2005-08-04

申请号：US11045786

申请日：2005-01-28

申请人： Koji Inoue ,  Yoshinao Morikawa ,  Atsushi Shimaoka ,  Yukio Tamai

发明人： Koji Inoue ,  Yoshinao Morikawa ,  Atsushi Shimaoka ,  Yukio Tamai

IPC分类号： G11C11/15 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08 ,  G11C11/00

CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.

摘要翻译： 半导体存储器件包括列读出电压供应电路，当选择读出时提供预定的第一电压，并且当未选择读出时将提供与第一电压不同的预定的第二电压提供给每列选择线，行读出 电压供给电路，其在读出时向每行行选择线提供第二电压;感测电路，其检测在所选行行选择线中流动的电流与流过未选择行选择线的电流分开，以检测电 在读出时所选择的存储单元的电阻状态和列电压位移防止电路，用于在读出时防止每个未选择的列选择线提供的电压电平的位移。

公开(公告)号：US07668001B2

公开(公告)日：2010-02-23

申请号：US11921755

申请日：2006-01-05

申请人： Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

发明人： Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

IPC分类号： G11C11/00

CPC分类号： G11C13/00 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77

摘要： A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array (100) so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array (100).

摘要翻译： 半导体存储器件（1）包括存储单元阵列（100），其中存储单元各自具有可变电阻元件，并且同一行中的存储单元连接到公共字线，并且同一列中的存储器单元被连接 公共位线，其中在预定的存储器动作期间，基于所选择的存储器单元的位置来调整施加到所选字线和所选位线中的至少一个的末端的电压脉冲的电压幅度 存储单元阵列（100），使得施加到要编程或擦除的所选存储单元的可变电阻元件的电压脉冲的有效电压幅度落在一定范围内，而与存储单元阵列（100）中的位置无关， 。

公开(公告)号：US20050151277A1

公开(公告)日：2005-07-14

申请号：US11035592

申请日：2005-01-13

申请人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Naoto Hagiwara ,  Hidetoshi Masuda ,  Toshimasa Suzuki

发明人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Naoto Hagiwara ,  Hidetoshi Masuda ,  Toshimasa Suzuki

IPC分类号： H01L27/105 ,  G11C13/00 ,  G11C16/02 ,  H01L27/115 ,  H01L27/24 ,  H01L45/00 ,  H01L27/11

CPC分类号： H01L27/2436 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/78 ,  G11C2213/79 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641

摘要： A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.

摘要翻译： 通过依次层叠下电极，可变电阻器和上电极来形成非易失性存储元件。 形成结晶性和非晶态混合的可变电阻器。 因此，形成非易失性存储元件。 更优选地，可变电阻器是由通式为Pr 1-x M x MnO 3 N 3表示的镨 - 钙 - 锰氧化物， 在350℃至500℃的成膜温度下形成的可变电阻器。或者，可变电阻器以允许可变电阻器变为非晶态的成膜温度或结晶度的状态形成为膜 并且将非晶化混合，然后在可变电阻器可以保持结晶性和非晶态混合的状态的温度范围内，在高于成膜温度的温度下进行退火处理。

公开(公告)号：US08869601B2

公开(公告)日：2014-10-28

申请号：US12976415

申请日：2010-12-22

申请人： Takeshi Yamamoto ,  Atsushi Shimaoka

发明人： Takeshi Yamamoto ,  Atsushi Shimaoka

IPC分类号： G01B5/12 ,  G01B5/28 ,  G01B5/012

CPC分类号： G01B5/012 ,  G01B5/28

摘要： A lever-type detector, a stylus, and an automatic stylus exchanger allow styluses of different types to be exchanged automatically and reduce the burden of exchanging the styluses of different types for the lever-type detector. An approximately U-shaped notch is formed in a seating plate provided for a stylus body. In order to attach a stylus to a stylus holder, the longitudinal direction of the stylus body is set in a direction orthogonal to the central axis of a shaft body of the stylus holder, and the seating plate is moved in the direction orthogonal to the central axis of the shaft body. Then, the notch guides the shaft body to the center of gravity of the whole stylus on the seating plate. With the shaft body guided to the center of gravity by the notch, a flat swinging member holds the seating plate detachably.

摘要翻译： 杠杆式检测器，触针和自动触针交换器允许自动交换不同类型的触笔，并且减轻了用于杠杆式检测器的不同类型的触笔的交换的负担。 在为触针本体提供的座板中形成大致U形的凹口。 为了将触针安装到触笔支架上，触针主体的纵向方向设置在与触笔支架的轴体的中心轴线正交的方向上，并且座板沿与中心正交的方向移动 轴体的轴线。 然后，切口将轴体引导到座板上整个触控笔的重心。 当轴体通过凹口引导到重心时，平坦的摆动构件可拆卸地保持座板。

公开(公告)号：US20100180458A1

公开(公告)日：2010-07-22

申请号：US12687456

申请日：2010-01-14

申请人： Atsushi Shimaoka ,  Takeshi Yamamoto

发明人： Atsushi Shimaoka ,  Takeshi Yamamoto

IPC分类号： G01B3/00 ,  F16C29/00

CPC分类号： G12B3/00

摘要： A linear guiding mechanism includes a fixed member, a moving member, a first double parallel leaf spring mechanism and a second double parallel leaf spring mechanism arranged between the fixed member and the moving member and configured to movably support the moving member. The first double parallel leaf spring mechanism and the second double parallel leaf spring mechanism are arranged at an angle other than 180° (for example, 90°) about an axis of movement of the moving member.

摘要翻译： 直线引导机构包括固定部件，移动部件，第一双平行板簧机构和布置在固定部件与移动部件之间的第二双平行板簧机构，并且构造成可移动地支撑移动部件。 第一双平行板簧机构和第二双平行板簧机构围绕移动构件的运动轴线以不同于180°（例如90°）的角度布置。

公开(公告)号：US07535746B2

公开(公告)日：2009-05-19

申请号：US11191900

申请日：2005-07-27

申请人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Hidenori Morimoto ,  Nobuyoshi Awaya

发明人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Hidenori Morimoto ,  Nobuyoshi Awaya

IPC分类号： G11C11/00

CPC分类号： G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  G11C2213/79

摘要： A nonvolatile semiconductor memory device according to the present invention comprises a memory cell selecting circuit for selecting the memory cell from the memory cell array in units of row, column or memory cell; a read voltage application circuit for applying a read voltage to the variable resistor element of the selected memory cells selected by the memory cell selecting circuit; and a read circuit for detecting the amount of the read current flowing in accordance with the resistance value of the variable resistor element with respect to the memory cell to be read of the selected memory cells and reading the information stored in the memory cell to be read; and the read voltage application circuit applies a dummy read voltage having reversed polarity from the read voltage to the variable resistor element of the selected memory cell.

摘要翻译： 根据本发明的非易失性半导体存储器件包括存储单元选择电路，用于以行，列或存储单元为单位从存储单元阵列中选择存储单元; 读取电压施加电路，用于对由存储单元选择电路选择的所选存储单元的可变电阻元件施加读取电压; 以及读取电路，用于根据可变电阻器元件的电阻值相对于要选择的存储器单元读取的存储单元检测流过的读取电流的量并读取存储在待读取的存储器单元中的信息 ; 并且读取电压施加电路将具有与读取电压相反的极性的虚拟读取电压施加到所选存储单元的可变电阻器元件。

公开(公告)号：US20090046495A1

公开(公告)日：2009-02-19

申请号：US11913490

申请日：2006-04-26

申请人： Atsushi Shimaoka ,  Hidechika Kawazoe ,  Yukio Tamai

发明人： Atsushi Shimaoka ,  Hidechika Kawazoe ,  Yukio Tamai

IPC分类号： G11C11/00 ,  G11C7/00

CPC分类号： G11C13/00 ,  G11C8/08 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0073 ,  G11C2013/009 ,  G11C2213/77 ,  H01L27/101

摘要： A nonvolatile semiconductor memory device comprises a memory cell selecting circuit which selects a selected memory cell (M0) from a memory cell array (3); and a programming voltage applying circuit, which applies a row programming voltage and a column programming voltage to a selected word line and a selected bit line, respectively, and applies a row programming blocking voltage and a column programming blocking voltage to unselected word lines and unselected bit lines, respectively, and applies a programming voltage sufficient for programming only on both ends of the selected memory (M0). The programming voltage applying circuit applies a programming compensating voltage having a polarity opposite to that of the voltage applied on both ends of the unselected memory cells (M1, M2) other than the selected memory cell (M0), on both ends of the unselected memory cells (M1, M2), while the programming voltage is applied to the selected memory cell (M0).

摘要翻译： 非易失性半导体存储器件包括从存储单元阵列（3）中选择所选存储单元（M0）的存储单元选择电路; 以及编程电压施加电路，其分别对所选择的字线和选定的位线施加行编程电压和列编程电压，并对未选择的字线和未选择的字线施加行编程阻止电压和列编程阻塞电压 并且仅在所选择的存储器（M0）的两端施加足以进行编程的编程电压。 编程电压施加电路施加与非选择存储器（M0）以外的未被选择的存储单元（M1，M2）的两端施加的电压极性相反的编程补偿电压，在未选择的存储器 而编程电压被施加到所选存储单元（M0）时，单元（M1，M2）。

公开(公告)号：US07283407B2

公开(公告)日：2007-10-16

申请号：US11045786

申请日：2005-01-28

申请人： Koji Inoue ,  Yoshinao Morikawa ,  Atsushi Shimaoka ,  Yukio Tamai

发明人： Koji Inoue ,  Yoshinao Morikawa ,  Atsushi Shimaoka ,  Yukio Tamai

IPC分类号： G11C7/00

CPC分类号： G11C7/062 ,  G11C7/06 ,  G11C7/12 ,  G11C7/14 ,  G11C8/08

摘要： A semiconductor memory device comprises a column readout voltage supply circuit which supplies a predetermined first voltage when readout is selected and supplies a predetermined second voltage which is different from the fist voltage when the readout is not selected, to each column selection line, a row readout voltage supply circuit which supplies the second voltage to each row selection line at the time of readout, a sense circuit which detects a current flowing in the selected row selection line separately from a current flowing in the non-selected row selection lines to detect an electric resistance state of the selected memory cell at the time of readout, and a column voltage displacement prevention circuit which prevents displacement of a supplied voltage level for each of the non-selected column selection lines at the time of readout.

摘要翻译： 半导体存储器件包括列读出电压供应电路，当选择读出时提供预定的第一电压，并且当未选择读出时将提供与第一电压不同的预定的第二电压提供给每列选择线，行读出 电压供给电路，其在读出时向每行行选择线提供第二电压;感测电路，其检测在所选行行选择线中流动的电流与流过未选择行选择线的电流分开，以检测电 在读出时所选择的存储单元的电阻状态和列电压位移防止电路，用于在读出时防止每个未选择的列选择线提供的电压电平的位移。

公开(公告)号：US07259387B2

公开(公告)日：2007-08-21

申请号：US11035592

申请日：2005-01-13

申请人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Naoto Hagiwara ,  Hidetoshi Masuda ,  Toshimasa Suzuki

发明人： Hidechika Kawazoe ,  Yukio Tamai ,  Atsushi Shimaoka ,  Naoto Hagiwara ,  Hidetoshi Masuda ,  Toshimasa Suzuki

IPC分类号： H01L47/00

CPC分类号： H01L27/2436 ,  G11C13/0007 ,  G11C13/003 ,  G11C2213/31 ,  G11C2213/78 ,  G11C2213/79 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1625 ,  H01L45/1641

摘要： A nonvolatile memory element is formed by layering a lower electrode, a variable resistor and an upper electrode in sequence. The variable resistor is formed in which crystallinity and amorphism are mixed. Thus, the nonvolatile memory element is formed. More preferably, the variable resistor is a praseodymium-calcium-manganese oxide represented by a general formula, Pr1-xCaxMnO3, that has been formed at a film forming temperature from 350° C. to 500° C. Alternatively, the variable resistor is formed as a film at a film forming temperature that allows the variable resistor to become of an amorphous state or a state where crystallinity and amorphism are mixed and, then, is subjected to an annealing process at a temperature higher than the film forming temperature, in a temperature range where the variable resistor can maintain the state where crystallinity and amorphism are mixed.

摘要翻译： 通过依次层叠下电极，可变电阻器和上电极来形成非易失性存储元件。 形成结晶性和非晶态混合的可变电阻器。 因此，形成非易失性存储元件。 更优选地，可变电阻器是由通式为Pr 1-x M x MnO 3 N 3表示的镨 - 钙 - 锰氧化物， 在350℃至500℃的成膜温度下形成的可变电阻器。或者，可变电阻器以允许可变电阻器变为非晶态的成膜温度或结晶度的状态形成为膜 并且将非晶化混合，然后在可变电阻器可以保持结晶性和非晶态混合的状态的温度范围内，在高于成膜温度的温度下进行退火处理。