公开(公告)号：US08692943B2

公开(公告)日：2014-04-08

申请号：US13524418

申请日：2012-06-15

Applicant: Moriyuki Tsuchihashi ,  Kohji Inoue ,  Susumu Hattori ,  Takaaki Sakurai ,  Yi Zeng

Inventor： Moriyuki Tsuchihashi ,  Kohji Inoue ,  Susumu Hattori ,  Takaaki Sakurai ,  Yi Zeng

IPC: G02F1/133 ,  G02F1/1343

CPC classification number: G02F1/13318 ,  G02F1/13338 ,  G02F2001/13312 ,  G02F2001/133388 ,  G06F1/1626 ,  G06F1/1637

Abstract: An electronic device having a liquid crystal shutter is disclosed. A liquid crystal shutter is provided in an area formed by expanding a liquid crystal display. The liquid crystal shutter includes a rear polarizer, a rear glass substrate, a segmented electrode, a liquid crystal, a counter electrode, a front glass substrate, a shutter aperture, and a front polarizer. A camera module is disposed behind the rear polarizer. A voltage applied to the segmented electrode can be controlled to visually expose or hide the lens of the camera module from a shutter aperture.

Abstract translation: 公开了一种具有液晶快门的电子设备。 在通过使液晶显示器膨胀形成的区域中设置液晶快门。 液晶快门包括后偏振器，后玻璃基板，分段电极，液晶，对电极，前玻璃基板，快门孔和前偏振器。 相机模块设置在后偏振器后面。 可以控制施加到分段电极的电压，以将摄像机模块的透镜从快门孔视觉曝光或隐藏。

公开(公告)号：US07952909B2

公开(公告)日：2011-05-31

申请号：US12517025

申请日：2007-11-05

Applicant: Kohji Inoue ,  Yasunari Hosoi ,  Shigeo Ohnishi ,  Nobuyoshi Awaya

Inventor： Kohji Inoue ,  Yasunari Hosoi ,  Shigeo Ohnishi ,  Nobuyoshi Awaya

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  G11C13/0026 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/72 ,  G11C2213/77 ,  G11C2213/79 ,  H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/1633

Abstract: Provided is a nonvolatile semiconductor device capable of performing writing operations of different resistance changes for memory cells having variable resistive elements whose resistive characteristics are changed by voltage applications, individually and simultaneously. The device includes: a load resistive characteristic variable circuit for each bit line connected commonly with the memory cells on the same column for selecting one of two load resistive characteristics according to a first writing operation where the resistive characteristics of the variable resistive element to be written transit from a low resistance state to a high resistance state or a second writing operation where they transit reversely; and a writing voltage pulse application circuit for applying a first voltage pulse in a first writing operation and a second voltage pulse in a second writing operation to the memory cells to be written through the load resistive characteristic variable circuits and the bit limes.

Abstract translation: 提供了一种非易失性半导体器件，其能够对具有可变电阻元件的存储单元进行不同的电阻变化的写入操作，该电阻元件的电阻特性单独并同时由电压应用而改变。 该装置包括：用于与同一列上的存储器单元共同连接的每个位线的负载电阻特性可变电路，用于根据要写入的可变电阻元件的电阻特性的第一写入操作来选择两个负载电阻特性中的一个 从低电阻状态转移到高电阻状态或其反向转发的第二写入操作; 以及写入电压脉冲施加电路，用于将第一写入操作中的第一电压脉冲和第二写入操作中的第二电压脉冲施加到要通过负载电阻特性可变电路和位灰分写入的存储单元。

公开(公告)号：US07683867B2

公开(公告)日：2010-03-23

申请号：US11336553

申请日：2006-01-20

Applicant: Kohji Inoue ,  Manabu Kodate ,  Keita Ishii ,  Rieko Kataoka

Inventor： Kohji Inoue ,  Manabu Kodate ,  Keita Ishii ,  Rieko Kataoka

IPC: G09G3/36

CPC classification number: G09G3/3611 ,  G09G5/06 ,  G09G2320/028 ,  G09G2320/0285 ,  G09G2320/068

Abstract: A system, method, and computer-usable medium are presented for controlling viewing angle characteristics by performing a color palette gradation control of a liquid crystal display, such that adjustment effects on a viewing angle range are improved.

Abstract translation: 呈现系统，方法和计算机可用介质，用于通过执行液晶显示器的调色板灰度控制来控制视角特性，从而提高对视角范围的调节效果。

公开(公告)号：US20090135641A1

公开(公告)日：2009-05-28

申请号：US11921755

申请日：2006-01-05

Applicant: Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

Inventor： Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

IPC: G11C11/00 ,  G11C5/14

CPC classification number: G11C13/00 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77

Abstract: A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array (100) so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array (100).

Abstract translation: 半导体存储器件（1）包括存储单元阵列（100），其中存储单元各自具有可变电阻元件，并且同一行中的存储单元连接到公共字线，并且同一列中的存储器单元被连接 公共位线，其中在预定的存储器动作期间，基于所选择的存储器单元的位置来调整施加到所选字线和所选位线中的至少一个的末端的电压脉冲的电压幅度 存储单元阵列（100），使得施加到要编程或擦除的所选存储单元的可变电阻元件的电压脉冲的有效电压幅度落在一定范围内，而与存储单元阵列（100）中的位置无关， 。

公开(公告)号：US07411811B2

公开(公告)日：2008-08-12

申请号：US11505411

申请日：2006-08-17

Applicant: Kohji Inoue

Inventor： Kohji Inoue

IPC: G11C11/00

CPC classification number: G11C8/08 ,  G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/31 ,  G11C2213/32 ,  G11C2213/34 ,  G11C2213/77

Abstract: In a semiconductor storage device with cross point type arrays of memory cells including variable resistor elements, a selected data line and unselected data lines are supplied with a row selecting potential and a row unselecting potential through a data line selecting transistor respectively, a selected bit line and unselected bit lines are supplied with a column selecting potential and a column unselecting potential through a bit line selecting transistor respectively. Data lines and bit lines are separately driven so that when the data line selecting transistor is higher in the current driving capability than the bit line selecting transistor, a second bias voltage between the row unselecting potential and column selecting potential is lower than a first bias voltage between the row selecting potential and column unselecting potential, in the opposite case, the first bias voltage is lower than the second voltage.

Abstract translation: 在具有包括可变电阻器元件的存储器单元的交叉点型阵列的半导体存储器件中，通过数据线选择晶体管分别向所选择的数据线和未选择的数据线提供具有行选择电位和行选择电位的选择位线 并且未选择的位线分别通过位线选择晶体管被提供有列选择电位和列选择电位。 分别驱动数据线和位线，使得当数据线选择晶体管的电流驱动能力高于位线选择晶体管时，行选择电位和列选择电位之间的第二偏置电压低于第一偏置电压 在行选择电位和列未选择电位之间，在相反的情况下，第一偏置电压低于第二电压。

公开(公告)号：US20060164329A1

公开(公告)日：2006-07-27

申请号：US11336553

申请日：2006-01-20

Applicant: Kohji Inoue ,  Manabu Kodate ,  Keita Ishii ,  Rieko Kataoka

Inventor： Kohji Inoue ,  Manabu Kodate ,  Keita Ishii ,  Rieko Kataoka

IPC: G09G5/00

CPC classification number: G09G3/3611 ,  G09G5/06 ,  G09G2320/028 ,  G09G2320/0285 ,  G09G2320/068

Abstract: A system, method, and computer-usable medium are presented for controlling viewing angle characteristics by performing a color palette gradation control of a liquid crystal display, such that adjustment effects on a viewing angle range are improved.

Abstract translation: 呈现系统，方法和计算机可用介质，用于通过执行液晶显示器的调色板灰度控制来控制视角特性，从而提高对视角范围的调节效果。

公开(公告)号：US07027322B2

公开(公告)日：2006-04-11

申请号：US10790238

申请日：2004-03-02

Applicant: Toshimasa Suzuki ,  Yuji Nishi ,  Masayuki Fujimoto ,  Nobuyoshi Awaya ,  Kohji Inoue ,  Keizo Sakiyama

Inventor： Toshimasa Suzuki ,  Yuji Nishi ,  Masayuki Fujimoto ,  Nobuyoshi Awaya ,  Kohji Inoue ,  Keizo Sakiyama

IPC: G11C11/00

CPC classification number: G11C13/0007 ,  B82Y10/00 ,  G11C2213/31 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1625

Abstract: There is provided an EPIR device which is excellent in mass productivity and high in practical utility.The EPIR device includes a lower electrode layer, a CMR thin film layer and an upper electrode layer which are laminated in this order on any of various substrates. A Pt polycrystal thin film 10 forming the lower electrode layer includes columnar Pt crystal grains 10A, 10B, 10C, . . . and over 90% of these crystal grains is oriented to a (1 1 1) face. Columnar PCMO crystal grain groups 20A, 20B, 20C, . . . are respectively locally grown epitaxially on the respective outermost surfaces of the Pt crystal grains 10A, 10B, 10C, . . . . Then, the crystal faces of the crystal grains included in the PCMO crystal grain groups 20A, 20B, 20C, . . . and vertical in the substrate surface normal direction are any one of (1 0 0)p, (1 1 0)p and (1 1 1)p planes.

Abstract translation: 提供了具有优异的批量生产率和高实用性的EPIR装置。 EPIR器件包括下列电极层，CMR薄膜层和上电极层，它们以任何各种衬底依次层叠。 形成下电极层的Pt多晶薄膜10包括柱状Pt晶粒10 A，10 B，10 C。 。 。 并且超过90％的这些晶粒取向为（111）面。 柱状PCMO晶粒组20 A，20 B，20 C， 。 。 分别在Pt晶粒10 A，10 B，10 C的各自的最外表面上外延地局部生长。 。 。 。 然后，包含在PCMO晶粒组20A，20B，20C中的晶粒的晶面。 。 。 并且在衬底表面法线方向上的垂直方向是（110）p1，（111）p1和（111）中的任何一个p < / SUB>飞机。

公开(公告)号：US09184856B2

公开(公告)日：2015-11-10

申请号：US11043235

申请日：2005-01-26

Applicant: Hideyuki Usui ,  Hideyuki Tagai ,  Osamu Yamamoto ,  Kohji Inoue ,  Kazuo Fujii ,  Kohhei Shibata

Inventor： Hideyuki Usui ,  Hideyuki Tagai ,  Osamu Yamamoto ,  Kohji Inoue ,  Kazuo Fujii ,  Kohhei Shibata

IPC: H04B1/00 ,  H04B15/00 ,  H04B15/02 ,  H04W16/14

CPC classification number: H04B15/02 ,  H04B2215/064 ,  H04W16/14

Abstract: Wireless noise is detected within a time period specifically held after a data packet is wirelessly communicated, where no data is purposefully wirelessly communicated during this time period. The time period may be an inter-frame space (IFS) period within which no data is to be wirelessly communicated, and that is a period waited for prior to accessing a wireless medium over which data is wirelessly communicated. One or more actions are performed to counteract the noise. The frequency at which a liquid crystal display is being driven may be decreased so that harmonics caused thereby that caused the noise are no longer within the wireless communication frequency range. An opposite-in-phase version of the noise may also or alternatively be combined with a signal when data is subsequently wirelessly received. The signal includes a data component and a noise component, the opposite-in-phase version of the noise canceling out the noise component.

Abstract translation: 在无线通信数据分组之后的特定时间段内检测无线噪声，在该时间段内没有有目的地无线地传送数据。 该时间段可以是不在其中无数据被无线传送的帧间空间（IFS）周期，并且这是在接入无线介质之前等待的时间段，数据被无线传送。 执行一个或多个动作来抵消噪声。 液晶显示器被驱动的频率可能会降低，从而导致噪声引起的谐波不再在无线通信频率范围内。 当数据随后被无线地接收时，噪声的相反相位版本也可以或者可选地与信号组合。 该信号包括数据分量和噪声分量，噪声的相反相位版本消除了噪声分量。

公开(公告)号：US20130063676A1

公开(公告)日：2013-03-14

申请号：US13524418

申请日：2012-06-15

Applicant: MORIYUKI TSUCHIHASHI ,  KOHJI INOUE ,  SUSUMU HATTORI ,  TAKAAKI SAKURAI ,  YI ZHENG

Inventor： MORIYUKI TSUCHIHASHI ,  KOHJI INOUE ,  SUSUMU HATTORI ,  TAKAAKI SAKURAI ,  YI ZHENG

IPC: G02F1/1333

CPC classification number: G02F1/13318 ,  G02F1/13338 ,  G02F2001/13312 ,  G02F2001/133388 ,  G06F1/1626 ,  G06F1/1637

Abstract: An electronic device having a liquid crystal shutter is disclosed. A liquid crystal shutter is provided in an area formed by expanding a liquid crystal display. The liquid crystal shutter includes a rear polarizer, a rear glass substrate, a segmented electrode, a liquid crystal, a counter electrode, a front glass substrate, a shutter aperture, and a front polarizer. A camera module is disposed behind the rear polarizer. A voltage applied to the segmented electrode can be controlled to visually expose or hide the lens of the camera module from a shutter aperture.

Abstract translation: 公开了一种具有液晶快门的电子设备。 在通过使液晶显示器膨胀形成的区域中设置液晶快门。 液晶快门包括后偏振器，后玻璃基板，分段电极，液晶，对电极，前玻璃基板，快门孔和前偏振器。 相机模块设置在后偏振器后面。 可以控制施加到分段电极的电压，以将摄像机模块的透镜从快门孔视觉曝光或隐藏。

公开(公告)号：US07668001B2

公开(公告)日：2010-02-23

申请号：US11921755

申请日：2006-01-05

Applicant: Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

Inventor： Masayuki Tajiri ,  Atsushi Shimaoka ,  Kohji Inoue

IPC: G11C11/00

CPC classification number: G11C13/00 ,  G11C13/0023 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/77

Abstract: A semiconductor memory device (1) comprises a memory cell array (100) in which memory cells each have a variable resistance element and the memory cells in the same row are connected to a common word line and the memory cells in the same column are connected to a common bit line, wherein during a predetermined memory action, the voltage amplitude of the voltage pulse applied to an end of at least one of the selected word line and the selected bit line is adjusted based on the position of the selected memory cell in the memory cell array (100) so that the effective voltage amplitude of a voltage pulse applied to the variable resistance element of the selected memory cell to be programmed or erased falls within a certain range regardless of the position in the memory cell array (100).

Abstract translation: 半导体存储器件（1）包括存储单元阵列（100），其中存储单元各自具有可变电阻元件，并且同一行中的存储单元连接到公共字线，并且同一列中的存储器单元被连接 公共位线，其中在预定的存储器动作期间，基于所选择的存储器单元的位置来调整施加到所选字线和所选位线中的至少一个的末端的电压脉冲的电压幅度 存储单元阵列（100），使得施加到要编程或擦除的所选存储单元的可变电阻元件的电压脉冲的有效电压幅度落在一定范围内，而与存储单元阵列（100）中的位置无关， 。