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公开(公告)号：US20240333300A1
公开(公告)日：2024-10-03
申请号：US18126924
申请日：2023-03-27
CPC分类号： H03M1/462 , H03M1/0607
摘要： An analog-to-digital converter (ADC) circuit includes a digital-to-analog converter (DAC) circuit, a comparator circuit, an encoder, and a compensation circuit. The DAC circuit receives a reference voltage and provides an output signal based on the reference voltage. The comparator circuit compares the output signal with an analog input signal and generates a comparison signal. A reset command is generated based on the output signal being greater than the analog input signal. The encoder splits a ripple associated with the reference voltage into multiple pulses in response to a reset command. The compensation circuit generates, responsive to the reset command, compensation pulses to compensate the multiple pulses.
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2.发明授权公开(公告)号：US11929756B2
公开(公告)日：2024-03-12
申请号：US17694225
申请日：2022-03-14
发明人： Yong Liu , Jun Cao , Delong Cui
CPC分类号： H03M1/1028 , H03M1/1009 , H03M1/1245 , H03M1/46
摘要： Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
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3.发明授权公开(公告)号：US10805002B2
公开(公告)日：2020-10-13
申请号：US15649430
申请日：2017-07-13
发明人： Yong Liu , Ron Porat , Nihar Jindal , Vinko Erceg , Matthew James Fischer , Chiu Ngok Eric Wong
摘要： A wireless communication device is implemented to include a communication interface and a processor. The processor is configured to process communications associated with the other wireless communication devices within the wireless communication system to determine one or more traffic characteristics of those communications as well as one or more class characteristics of the other wireless communication devices. The processor is configured to classify the communications into one or more access categories based on the one or more traffic characteristics and is configured to classify the other devices into one or more device class categories based on the one or more class characteristics. The processor is then configured to generate one or more channel access control signals based on these classifications. The communication interface of the device is configured to transmit the one or more channel access control signals to one or more of the other devices.
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公开(公告)号：US20240257847A1
公开(公告)日：2024-08-01
申请号：US18103696
申请日：2023-01-31
发明人： Vadim Milirud , Guansheng Li , Seong-Ho Lee , Jun Cao , Yong Liu
CPC分类号： G11C7/16 , G11C7/1039 , G11C7/222
摘要： Described herein are systems and methods related to a device including an analog-to-digital converter (DAC) configured to convert a digital signal into an analog signal. The systems and methods can receive an analog signal at a first input, and provide the analog signal to a first output in response to a first clock signal. The first clock signal has a level at least partially dependent on the analog signal. The systems and methods can provide a path to a ground node for the first clock signal in response to a second clock signal. The second clock signal is independent of the analog signal.
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5.发明公开公开(公告)号：US20230291411A1
公开(公告)日：2023-09-14
申请号：US17694225
申请日：2022-03-14
发明人： Yong Liu , Jun Cao , Delong Cui
IPC分类号： H03M1/10
CPC分类号： H03M1/1028
摘要： Disclosed herein are related to systems and methods for a successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of the plurality of bits corresponding to the input voltage and accumulates or averages at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, a second offset signal to control a second offset associated with a second comparator, or reduce an offset difference associated with the first offset and the second offset.
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公开(公告)号：US20230353173A1
公开(公告)日：2023-11-02
申请号：US17733219
申请日：2022-04-29
发明人： Xiaochen Yang , Hamid Hatamkhani , Guansheng Li , Yong Liu , Delong Cui , Jun Cao
CPC分类号： H04B1/04 , H04B1/0003 , H04B2001/0425 , H04B2001/0416
摘要： Novel tools and techniques are provided for implementing a novel integrated programmable gain amplifier (“PGA”) and protection circuit. In various embodiments, a circuit is provided that comprises: a PGA, an analog-to-digital converter (“ADC”), and a protection circuit all disposed on the same semiconductor chip. The PGA is configured to receive as input a wireless signal received from an antenna and to output, at its output, an amplified wireless signal based on the wireless signal being amplified by a programmable gain amount. The protection circuit is configured to, in response to detecting a spike in gain at the output of the PGA that exceeds a threshold amplitude, control a decrease in the programmable gain amount to cause a resultant signal at the output of the PGA to be below the threshold amplitude. A normally-open switch may also be added at differential outputs of the PGA to further clamp PGA output.
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公开(公告)号：US10903846B1
公开(公告)日：2021-01-26
申请号：US16867358
申请日：2020-05-05
发明人： Yong Liu , Delong Cui , Jun Cao
摘要： Disclosed herein are related to systems and methods for a power efficient successive approximation analog to digital converter (SAR ADC). In one aspect, the SAR ADC includes a sample and digital to analog conversion (DAC) circuit to sample an input voltage. In one aspect, the SAR ADC includes a first comparator coupled to the DAC circuit, and a first set of storage circuits coupled between the first comparator and the DAC circuit. In one aspect, the SAR ADC includes a second comparator coupled to the DAC circuit, and a second set of storage circuits coupled between the second comparator and the DAC circuit. In one aspect, the SAR ADC includes a control circuit configured to select, for each of multiple bits corresponding to the input voltage, a corresponding comparator to determine a state of the each of the multiple bits during a corresponding time period.
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公开(公告)号：US10541679B1
公开(公告)日：2020-01-21
申请号：US16170068
申请日：2018-10-25
发明人： Yong Liu , Chang Liu , Delong Cui , Jun Cao
IPC分类号： H03K3/356 , H03K17/082
摘要： Various aspects of amplifying amplitude of a pulse are disclosed herein. In sonic embodiments, a device includes driver circuitry that receives an input pulse swinging or transitioning between a first reference voltage and a second reference voltage higher than the first reference voltage, In some embodiments, the driver circuitry generates a driving pulse swinging between a third reference voltage and the second reference voltage according to the input pulse, where the third reference voltage is between the first reference voltage and the second reference voltage. In some embodiments, the device further includes a transistor coupled to the driver circuitry. In some embodiments, the transistor outputs an output pulse swinging between the first reference voltage and an output voltage according to the driving pulse from the driver circuitry, where the output voltage is higher than the second reference voltage.
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