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公开(公告)号：US20090237280A1
公开(公告)日：2009-09-24
申请号：US12475841
申请日：2009-06-01
Applicant: Benjamin H. Ashmore, JR.
Inventor： Benjamin H. Ashmore, JR.
IPC: H03M1/10
Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
Abstract translation: 公开了用于操作转换器或其它电路的方法，系统和装置。 更具体地，在一个实施例中，转换器或其他电路可以以两种模式操作，这两种模式可以包括计数到时间和时间计数模式以确定对应于输入信号的输出值。 在计数到时间模式的操作期间，可以使用参考信号来操作转换器，以确定所需的时钟周期数，直到输出对应于缩放因子为止。 在时间到计数模式下的电路操作期间，转换器可以使用输入信号来操作这个数量的时钟周期，以确定输出。 该输出可能与输入信号上的电平成比例。
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公开(公告)号：US07069485B2
公开(公告)日：2006-06-27
申请号：US10695606
申请日：2003-10-28
Applicant: Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
Inventor： Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
IPC: G01R31/3158
CPC classification number: G01R31/318572 , G11C29/32 , G11C29/48 , G11C2029/3202
Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included in circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple TAP read or write operations operations.
Abstract translation: 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路中，使得可以将串行数据写入存储器并从存储器写入，而不必重复地循环通过多个TAP读取或写入操作操作。
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公开(公告)号：US06675333B1
公开(公告)日：2004-01-06
申请号：US09718206
申请日：2000-11-21
Applicant: Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
Inventor： Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
IPC: G01R313185
CPC classification number: G01R31/318572 , G11C29/32 , G11C29/48 , G11C2029/3202
Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
Abstract translation: 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路上，使得串行数据可以被写入存储器并从存储器写入，而不必重复地循环通过多个移位操作。
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公开(公告)号：US5687179A
公开(公告)日：1997-11-11
申请号：US415121
申请日：1995-03-29
Applicant: Lee D. Whetsel, Jr. , Benjamin H. Ashmore, Jr.
Inventor： Lee D. Whetsel, Jr. , Benjamin H. Ashmore, Jr.
IPC: G06F13/38 , G01R31/3185 , G11C29/32
CPC classification number: G01R31/318558 , G11C29/32
Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
Abstract translation: 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路上，使得串行数据可以被写入存储器并从存储器写入，而不必重复地循环通过多个移位操作。
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公开(公告)号：US09344109B2
公开(公告)日：2016-05-17
申请号：US14642436
申请日：2015-03-09
Applicant: Benjamin H. Ashmore, Jr.
Inventor： Benjamin H. Ashmore, Jr.
Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
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Patent Agency Ranking
公开(公告)号：US09013338B2
公开(公告)日：2015-04-21
申请号：US13529787
申请日：2012-06-21
Applicant: Benjamin H. Ashmore, Jr.
Inventor： Benjamin H. Ashmore, Jr.
Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
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公开(公告)号：US06158035A
公开(公告)日：2000-12-05
申请号：US320491
申请日：1999-05-26
Applicant: Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
Inventor： Lee Doyle Whetsel, Jr. , Benjamin H. Ashmore, Jr.
IPC: G06F13/38 , G01R31/3185 , G11C29/32
CPC classification number: G01R31/318558 , G11C29/32
Abstract: A serial scan path communication architecture includes a plurality of circuits (30), some of which may include a memory (36). A memory access controller (38) is included on circuits with a memory (36) such that serial data may be written to and written from the memories without having to repetitively cycle through multiple shift operations.
Abstract translation: 串行扫描路径通信架构包括多个电路（30），其中一些电路可以包括存储器（36）。 存储器访问控制器（38）包括在具有存储器（36）的电路上，使得串行数据可以被写入存储器并从存储器写入，而不必重复地循环通过多个移位操作。
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8.发明授权
公开(公告)号：US4866307A
公开(公告)日：1989-09-12
申请号：US183956
申请日：1988-04-20
Applicant: Benjamin H. Ashmore, Jr.
Inventor： Benjamin H. Ashmore, Jr.
CPC classification number: G11C16/045 , G11C16/0408 , G11C16/0441 , G11C16/10 , G11C2216/10
Abstract: A zero-power bit circuit comprised in part of a pair of single-level poly transistors having opposite impurity-type channels, the pair connected to accomplish the programming function of a floating-gate transistor. The circuit includes sensing transistors for sensing the presence of absence of charge on the commonly connected gates of a transistor quadruplet comprised of the programming pair and sensing transistors. A diode-connected transistor, an isolation transistor and an inverter-buffer are also included in the bit circuit.
Abstract translation: 零功率位电路包括一对具有相对杂质型沟道的单级多晶硅晶体的一部分，该对连接以实现浮栅晶体管的编程功能。 该电路包括用于感测在由编程对和感测晶体管组成的晶体管四极管的共同连接的栅极上存在电荷的感测晶体管。 二极管连接的晶体管，隔离晶体管和反相器缓冲器也包含在位电路中。
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公开(公告)号：US4862019A
公开(公告)日：1989-08-29
申请号：US183958
申请日：1988-04-20
Applicant: Benjamin H. Ashmore, Jr.
Inventor： Benjamin H. Ashmore, Jr.
Abstract: A zero-power bit circuit comprised in part of a pair of single-level poly transistors with opposite impurity-type channels, the pair connected to accomplish the programming function of a floating-gate transistor. The circuit includes three programming/isolating transistors and an inverter-buffer.
Abstract translation: 一个零功率位电路包括在具有相对杂质型沟道的一对单级多晶硅晶体管的一部分中，该对连接以实现浮栅晶体管的编程功能。 该电路包括三个编程/隔离晶体管和一个逆变器缓冲器。
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公开(公告)号：US20160308552A1
公开(公告)日：2016-10-20
申请号：US15132716
申请日：2016-04-19
Applicant: Benjamin H. Ashmore, JR.
Inventor： Benjamin H. Ashmore, JR.
IPC: H03M3/00
Abstract: Methods, systems and apparatuses for operating a converter or other circuits are disclosed. More particularly, in one embodiment a converter or other circuit can be operated in two modes which may include the count-to-time and time-to count modes to determine an output value corresponding to an input signal. During operation in the count-to-time mode a converter may be operated using a reference signal to determine a number of clock cycles needed until an output corresponds to a scaling factor is reached. During operation of the circuit in the time-to-count mode then, the converter may be operated for this number of clock cycles using the input signal to determine an output. This output may be proportional to the level on the input signal.
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