公开(公告)号：US06233717B1

公开(公告)日：2001-05-15

申请号：US09216198

申请日：1998-12-18

申请人： Byeng-Sun Choi

发明人： Byeng-Sun Choi

IPC分类号： G11C2900

CPC分类号： G11C11/56 ,  G06F11/1072 ,  G11C11/5692 ,  G11C29/00 ,  G11C2211/5642

摘要： An integrated circuit multi-bit memory device incorporating an error check and correction (ECC) technique is provided. In the error correction, two or more groups of parity bits corresponding to a data word of the multi-bit memory device are programmed therein. The groups are classified by the number of bits per cell. Error bits in a memory data word are checked sequentially by the group, and the checked error bits are also corrected sequentially by the group, thereby preventing the device failure due to two or more errors in a data word of the multi-bit memory device.

摘要翻译： 提供了一种结合错误检查和校正（ECC）技术的集成电路多位存储器件。 在纠错中，与多位存储器件的数据字对应的两组或多组奇偶校验位被编程在其中。 这些组按照每个单元的位数进行分类。 存储器数据字中的错误位由组被顺序地检查，并且所检查的错误位也被组顺序校正，从而防止由于多位存储器件的数据字中的两个或更多个错误引起的器件故障。

公开(公告)号：US6137726A

公开(公告)日：2000-10-24

申请号：US198705

申请日：1998-11-24

申请人： Byeng-Sun Choi ,  Young-Ho Lim

发明人： Byeng-Sun Choi ,  Young-Ho Lim

IPC分类号： G11C16/04 ,  G11C11/56 ,  G11C16/02 ,  G11C16/06 ,  G11C16/30

CPC分类号： G11C16/30 ,  G11C11/5621 ,  G11C16/08 ,  G11C8/14

摘要： A plurality of memory cell referenced regulators is connected to an output terminal that is configured to connect to a plurality of memory cells of a multi-level memory device. A respective one of the memory cell referenced regulators includes a respective dummy memory cell having a respective predetermined threshold voltage. The plurality of memory cell referenced regulators are responsive to a select signal such that a selected one of the memory cell referenced regulators varies a current at the output terminal to maintain the output terminal at a voltage proportional to the threshold voltage of the dummy memory cell of the selected memory cell referenced regulator. Each of the memory cell referenced regulators may comprise a variable current mirror having a controlled current path and an output current path including the output terminal. The controlled current path includes a controlled impedance therein that provides a variable impedance responsive to a control voltage applied thereto such that current produced at the output terminal is proportional to current in the controlled current path. A control voltage generator is connected between the output terminal and the controlled impedance and includes a dummy memory cell having a predetermined threshold voltage. The control voltage generator is operative to apply a control voltage to the controlled impedance to vary a current at the output terminal when an output voltage at the output terminal is greater than a predetermined voltage proportional to the predetermined threshold voltage of the dummy memory cell.

摘要翻译： 多个存储单元参考调节器连接到被配置为连接到多级存储器件的多个存储器单元的输出端子。 存储单元参考调节器中的相应一个包括具有相应的预定阈值电压的相应的虚拟存储单元。 多个存储器单元参考的调节器响应于选择信号，使得所选择的存储单元参考调节器中的一个调节器改变输出端子处的电流，以将输出端子保持在与虚拟存储器单元的阈值电压成正比的电压 所选存储单元参考调节器。 每个存储单元参考的调节器可以包括具有受控电流路径的可变电流镜和包括输出端的输出电流路径。 受控电流路径包括其中的受控阻抗，其响应于施加到其上的控制电压提供可变阻抗，使得在输出端产生的电流与受控电流路径中的电流成比例。 控制电压发生器连接在输出端子和受控阻抗之间，并且包括具有预定阈值电压的虚拟存储单元。 当输出端子处的输出电压大于与虚拟存储器单元的预定阈值电压成比例的预定电压时，控制电压发生器可操作以将控制电压施加到受控阻抗以改变输出端子处的电流。

公开(公告)号：US5923586A

公开(公告)日：1999-07-13

申请号：US964521

申请日：1997-11-05

申请人： Byeng-sun Choi

发明人： Byeng-sun Choi

IPC分类号： G11C16/02 ,  G11C16/22 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  G11C7/00

CPC分类号： G11C16/22

摘要： Disclosed is a nonvolatile memory having lockable cell array. The memory includes a lockable cell array formed of a plurality of lockable cell transistors and lockable word lines coupled to gates of the lockable cell transistors; and a lockable pass transistor array formed of a plurality of lockable pass transistors connecting the lockable word lines to a plurality of selection signals. The lockable word lines are coupled to boosting elements which are in response to capacitive coupling in a bulk during an unlock operation.

摘要翻译： 公开了具有可锁定单元阵列的非易失性存储器。 存储器包括由多个可锁定单元晶体管形成的可锁定单元阵列和耦合到可锁定单元晶体管的栅极的可锁定字线; 以及由将可锁定字线连接到多个选择信号的多个可锁定通过晶体管形成的可锁定晶体管阵列。 可锁定字线耦合到在解锁操作期间响应于大容量电容耦合的升压元件。

公开(公告)号：US06324115B1

公开(公告)日：2001-11-27

申请号：US09520730

申请日：2000-03-08

申请人： Byeng-Sun Choi

发明人： Byeng-Sun Choi

IPC分类号： G11C800

CPC分类号： G11C7/06 ,  G11C7/1018 ,  G11C8/18

摘要： A data sensing control circuit according to the present invention is provided in a semiconductor memory device with a burst access mode. The data sensing control circuit generates sensing control signals for data sensing operation by use of a transition information of an address bit signal synchronized with a read enable clock signal and used for a bank selection. According to such a data sensing control scheme, no sensing of each sensing period is performed when the read enable clock signal transitions. Therefore, a power noise (or input/output noise) issued at data-out does not affect the data sensing operation of the semiconductor memory device having the burst access mode.

摘要翻译： 根据本发明的数据感测控制电路设置在具有突发存取模式的半导体存储器件中。 数据感测控制电路通过使用与读使能时钟信号同步并用于存储体选择的地址位信号的转移信息来产生用于数据检测操作的感测控制信号。 根据这种数据感测控制方案，当读使能时钟信号转换时，不执行每个感测周期的感测。 因此，在数据输出时发出的功率噪声（或输入/输出噪声）不影响具有突发存取模式的半导体存储器件的数据感测操作。

公开(公告)号：US5949727A

公开(公告)日：1999-09-07

申请号：US6290

申请日：1998-01-13

申请人： Byeng-Sun Choi ,  Young-ho Lim

发明人： Byeng-Sun Choi ,  Young-ho Lim

IPC分类号： G11C17/18 ,  G11C7/00 ,  G11C7/12 ,  G11C16/06

CPC分类号： G11C7/12

摘要： A semiconductor memory device includes a precharge circuit for precharging bit lines responsive to a first control signal during a bit line precharge period and a plurality of transistors each having a current path connected between the corresponding bit line and the precharge circuit. The memory device also includes a control terminal for receiving a second control signal, a data sensing circuit for sensing data states on the bit lines during a data sensing period, and a control circuit for generating the first and second control signals. The second control signal has a first and a second voltage levels during the bit line precharge period and the data sensing period, respectively. The first voltage level is different from the second voltage level. As a result, the corresponding sensing node between the transistors and the data sensing means is maintained to a preset voltage without transitorily dropping during a data sensing period. The second control signal changes to the second voltage level during the bit line precharge period. By doing so, the bit line voltage does not momentarily drop owing to inter-bit line capacitive coupling and the corresponding sensing node maintains its preset voltage level during the data sensing period.

摘要翻译： 半导体存储器件包括预充电电路，用于在位线预充电周期期间响应于第一控制信号对位线进行预充电，以及每个具有连接在相应位线和预充电电路之间的电流通路的多个晶体管。 存储装置还包括用于接收第二控制信号的控制端子，用于在数据感测期间感测位线上的数据状态的数据感测电路，以及用于产生第一和第二控制信号的控制电路。 第二控制信号在位线预充电期间和数据检测期间分别具有第一和第二电压电平。 第一电压电平与第二电压电平不同。 结果，晶体管和数据感测装置之间的对应的感测节点在数据感测期间内不会被瞬时下降地维持在预设电压。 在位线预充电期间，第二控制信号变为第二电压电平。 通过这样做，由于位线间电容耦合，位线电压不会瞬间下降，并且相应的感测节点在数据感测期间保持其预设电压电平。

公开(公告)号：US06226214B1

公开(公告)日：2001-05-01

申请号：US09082060

申请日：1998-05-21

申请人： Byeng-Sun Choi

发明人： Byeng-Sun Choi

IPC分类号： G11C800

CPC分类号： G11C17/126 ,  G11C7/18

摘要： The disclosed is a read only memory having a plurality of memory blocks each associated with main bit lines and sub-bit lines, and a plurality of memory cells for storing information, and sense amplifiers for reading the information stored in the memory cells through the main bit lines. The memory also has a block selection part disposed between the blocks and having a plurality of block selection transistors connecting the main bit lines to the sub-bit lines. The sub-bit lines elongate to at least an adjacent block and alternatively connected to the main bit lines through the block selection part.

摘要翻译： 所公开的是具有多个与主位线和子位线相关联的多个存储块的只读存储器，以及用于存储信息的多个存储单元，以及用于通过主器件读取存储在存储器单元中的信息的读出放大器 位线。 存储器还具有布置在块之间的块选择部分，并且具有将主位线连接到子位线的多个块选择晶体管。 子位线延伸到至少相邻的块，并且可选地通过块选择部连接到主位线。

公开(公告)号：US6088277A

公开(公告)日：2000-07-11

申请号：US340556

申请日：1999-06-28

申请人： Kang-Young Kim ,  Byeng-Sun Choi

发明人： Kang-Young Kim ,  Byeng-Sun Choi

IPC分类号： G11C16/06 ,  G11C7/06 ,  G11C7/10 ,  G11C7/12 ,  G11C17/06 ,  G11C17/12 ,  G11C7/00

CPC分类号： G11C7/12 ,  G11C17/126 ,  G11C7/065 ,  G11C7/1006

摘要： A read-only memory device having a NOR structure is provided. The memory device comprises a memory cell array having a plurality of memory cells, each memory cell storing data, a plurality of first bit lines coupled to the array, and a plurality of second bit lines coupled to the array. A first selection circuit are coupled to the plurality of first bit lines for selecting at least two adjacent first bit lines. A second selection circuit coupled to the plurality of second bit lines for selecting at least two adjacent second bit lines. A sense amplification circuit detect a cell state of a selected memory cell by biasing the selected first bit lines and one of the selected second bit lines with a same potential. The second selection circuit grounds another of the selected second bit lines. The first selection circuit grounds unselected first bit lines and wherein the second selection circuit grounds unselected second bit lines. According to the mask ROM of the present invention, leakage current paths to the biased main and ground bit lines are cut off during a data reading operation of an off-cell. The biased main and ground bit lines can be charged by only one sense amplification circuit.

摘要翻译： 提供具有NOR结构的只读存储器件。 存储器件包括具有多个存储器单元的存储单元阵列，每个存储单元存储数据，耦合到阵列的多个第一位线以及耦合到阵列的多个第二位线。 第一选择电路耦合到多个第一位线，用于选择至少两个相邻的第一位线。 耦合到所述多个第二位线的第二选择电路，用于选择至少两个相邻的第二位线。 感测放大电路通过偏置所选择的第一位线和所选择的第二位线之一以相同的电位来检测所选存储单元的单元状态。 第二选择电路接地另一个选定的第二位线。 第一选择电路接地未选择的第一位线，并且其中第二选择电路接地未选择的第二位线。 根据本发明的掩模ROM，在离电池的数据读取操作期间，切断偏置的主位线和接地位线的漏电流路径。 偏置的主位线和地线位线只能由一个读出放大电路充电。

公开(公告)号：US5963475A

公开(公告)日：1999-10-05

申请号：US990023

申请日：1997-12-12

申请人： Byeng-Sun Choi ,  Tae-Sung Jung ,  Myoung-Jae Kim ,  Seung-Keun Lee

发明人： Byeng-Sun Choi ,  Tae-Sung Jung ,  Myoung-Jae Kim ,  Seung-Keun Lee

IPC分类号： G11C16/02 ,  G11C8/12 ,  G11C16/04 ,  G11C16/06 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/34 ,  G11C8/12

摘要： Disclosed is a nonvolatile memory, compatible with a dynamic random access memory, including a memory array divided into a plurality of blocks, each of the blocks being divided into a plurality of sub-blocks, reading and writing row decoders for selecting rows of the memory array, and reading and writing gate drive circuits for selecting a plurality of drive lines which supply source voltages to the rows of the memory array, wherein the memory array employs a plurality of section decoders which are arranged between the sub-blocks, each of the section decoders being assigned to a half of the rows belong to the sub-block and connecting the drive lines to the rows.

摘要翻译： 公开了一种与动态随机存取存储器兼容的非易失性存储器，包括被划分为多个块的存储器阵列，每个块被分成多个子块，读取和写入行解码器，用于选择存储器的行 阵列和用于选择向存储器阵列的行提供源电压的多个驱动线的读写栅极驱动电路，其中存储器阵列采用布置在子块之间的多个部分解码器， 分配给一半行的段解码器属于子块并将驱动线连接到行。

公开(公告)号：US5677873A

公开(公告)日：1997-10-14

申请号：US716022

申请日：1996-09-19

申请人： Byeng-Sun Choi ,  Tae-Sung Jung

发明人： Byeng-Sun Choi ,  Tae-Sung Jung

IPC分类号： G11C17/00 ,  G11C16/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  G11C11/34

CPC分类号： G11C16/0483 ,  G11C16/10

摘要： Methods of programming flash EEPROM integrated circuit memory devices containing an array of NAND cells therein include the steps of applying a preselected logic signal to a select transistor of a NAND memory cell to inhibit the likelihood of inadvertent programming thereof when adjacent cells are being programmed. According to one embodiment, a first logic signal having a first non-zero potential (V.sub.fp) is applied to a bit line BL of a first NAND memory cell in the array. Then, at commencement of a first time interval (TI), a second logic signal having a second potential which is greater than the first potential is applied to the gate (SSL) of the first select transistor ST1 to thereby turn-on the first select transistor "hard" and drive the potential of a source (S) thereof towards the potential of the bit line (i.e., V.sub.fp). Here, the first potential V.sub.fp is preferably selected to be higher than the power supply voltage VCC. Then, upon termination of the first time interval TI, the potential of the second bilevel logic signal is reduced from the second potential to the first potential V.sub.fp (or ground GND) to thereby limit conduction across the channel of the first select transistor ST1 and electrically isolate the bit line BL from the source, drain and channel regions of the EEPROM transistors in the first NAND memory cell. Preferably following termination of the first time interval, a pass logic signal having a pass potential (V.sub.pass) and a program logic signal having a program potential (V.sub.pgm) (where V.sub.pgm >V.sub.pass) are applied to the gates of a plurality of unselected EEPROM transistors and the gate of a "selected" EEPROM transistor in the first NAND memory cell.

摘要翻译： 编程包含其中NAND单元阵列的快闪EEPROM集成电路存储器件的方法包括以下步骤：将预选逻辑信号施加到NAND存储器单元的选择晶体管，以在相邻单元被编程时抑制其无意编程的可能性。 根据一个实施例，具有第一非零电位（Vfp）的第一逻辑信号被施加到阵列中的第一NAND存储器单元的位线BL。 然后，在第一时间间隔（TI）开始时，将具有大于第一电位的第二电位的第二逻辑信号施加到第一选择晶体管ST1的栅极（SSL），从而接通第一选择 晶体管“硬”并且将其源极（S）的电位驱动到位线的电位（即，Vfp）。 这里，优选选择第一电位Vfp高于电源电压VCC。 然后，在第一时间间隔TI终止时，第二二级逻辑信号的电位从第二电位减小到第一电位Vfp（或接地GND），从而限制第一选择晶体管ST1的沟道的导通， 将位线BL与第一NAND存储器单元中的EEPROM晶体管的源极，漏极和沟道区隔离。 优选地，在第一时间间隔结束之后，将具有通过电位（Vpass）和具有编程电位（Vpgm）（Vpgm> Vpass）的编程逻辑信号的通过逻辑信号施加到多个未选择的EEPROM晶体管的栅极 以及第一NAND存储器单元中的“选择”EEPROM晶体管的栅极。

公开(公告)号：US06252817B1

公开(公告)日：2001-06-26

申请号：US09361490

申请日：1999-07-26

申请人： Yong-Seok Seo ,  Byeng-Sun Choi

发明人： Yong-Seok Seo ,  Byeng-Sun Choi

IPC分类号： G11C800

CPC分类号： G11C8/12

摘要： A memory comprising a plurality of memory blocks having a plurality of memory cells and wordlines, each of the memory blocks having selection lines by which the memory blocks are selected. The selection lines are shared between neighboring blocks. In addition, a wordline switching circuit is coupled between conductors carrying wordline drive signals and the wordlines, and a block selection line circuit is coupled between conductors carrying the block selection lines signals and the block selection lines. A selection control circuit supplies selection control signals to the wordline switching circuit and the block selection line switching circuit. The selection control circuit generates the selection control signals in response to address informing signals. The selection lines are coupled to discharge circuits, which pull down voltage levels of selection lines that are not selected.

摘要翻译： 一种存储器，包括具有多个存储器单元和字线的多个存储器块，每个存储器块具有选择存储块的选择线。 选择行在相邻块之间共享。 此外，字线切换电路耦合在承载字线驱动信号和字线的导体之间，并且块选择线电路耦合在承载块选择线信号的导体和块选择线之间。 选择控制电路将选择控制信号提供给字线切换电路和块选择线切换电路。 选择控制电路响应于地址通知信号产生选择控制信号。 选择线耦合到放电电路，其降低未被选择的选择线的电压电平。